Abstract: Selectively implanting carbon in a transistor lowers the collector-to-emitter breakdown (BVCEO) of the transistor. This transistor, with the lowered BVCEO, is then used as a “trigger” device in an Electrostatic Discharge (ESD) power clamp comprising a first low breakdown trigger device and a second high breakdown clamp device. ESD power clamps are constructed using epitaxial base pseudomorphic Silicon Germanium heterojunction transistors in a common-collector Darlington configuration.

Abstract: A semiconductor substrate includes a first principal plane and a second principal plane opposite this first principal plane. A first semiconductor region is formed on the first principal plane of the semiconductor substrate. Second and third semiconductor regions are formed separately from each other on the first semiconductor region. A gate electrode is formed, via a gate insulator, on the first semiconductor region between the second semiconductor region and the third semiconductor region. An electric conductor is formed up to the semiconductor substrate from the second semiconductor region and electrically connects the second semiconductor region with the semiconductor substrate. A first main electrode is formed on the second principal plane of the semiconductor substrate and is electrically connected to the semiconductor substrate. A second main electrode is formed on the first semiconductor region via insulators and is electrically connected to the third semiconductor region.

Abstract: Electrically, thermally and mechanically enhanced ball grid array (BGA) packages are described. An IC die is mounted to a first surface of a first stiffener. A peripheral edge portion of a second surface of the first stiffener is attached to a first surface of a second stiffener to cover an opening through the second stiffener that is open at the first surface and a second surface of the second stiffener. The second surface of the second stiffener is attached to a first surface of a substantially planar substrate that has a plurality of contact pads on the first surface of the substrate. The plurality of contact pads are electrically connected through the substrate to a plurality of solder ball pads on a second surface of the substrate.

Abstract: The radio frequency (RF) impedance of a metal trace at gigahertz frequencies is reduced by forming the metal trace to have a base region and a number of fins that extend away from the base region. When formed in a spiral configuration having a number of loops, the metal trace forms an inductor with an increased quality factor (Q).

Abstract: A 3-D spiral stacked inductor is provided having a substrate with a plurality of turns in a plurality of levels wherein the number of levels increases from an inner turn to the outer turn of the inductor. First and second connecting portions are respectively connected to an inner turn and an outermost turn, and dielectric material contains the first and second connecting portions and the plurality of turns over the substrate.

Abstract: A high frequency switch, has a transmitting terminal; a receiving terminal; an antenna terminal; a first diode having an anode electrically connected to the transmitting terminal and a cathode electrically connected to the antenna terminal; a second diode having an anode connected through a transmission line of ¼ wavelength to the antenna terminal which is electrically connected to the receiving terminal, and having the side of a cathode grounded; and a control terminal provided to a node between the transmitting terminal and the first anode, wherein the first and second diodes have a tradeoff relationship between ON resistance thereof and capacitance between the anode and the cathode, and the ON resistance of the first diode is lower than the ON resistance of the second diode, and the capacitance of the second diode in the OFF state is smaller than the capacitance of the first diode in the OFF state.

Abstract: A non-volatile memory cell includes a first insulating layer over a substrate region, and a floating gate. The floating gate includes a first polysilicon layer over the first insulating layer and a second polysilicon layer over and in contact with the first polysilicon layer. The first polysilicon layer has a predetermined doping concentration and the second polysilicon layer has a doping concentration which decreases in a direction away from an interface between the first and second polysilicon layers. A second insulating layer overlies and is in contact with the second polysilicon layer. A control gate includes a third polysilicon layer over and in contact with the second insulating layer, and a fourth polysilicon layer over and in contact with the third polysilicon layer. The fourth polysilicon layer has a predetermined doping concentration, and the third polysilicon layer has a doping concentration which decreases in a direction away from an interface between the third and fourth polysilicon layers.

Abstract: A semiconductor device includes an electrically insulating board; conductive interconnections formed on a first face of the board and on a second face opposite to the first face; a semiconductor chip fixed to the board through at least the interconnections on the first face, said semiconductor chip having a semiconductor element electrically connected to the interconnections; a conductive bump formed on the second face of the board and electrically connected to the interconnections on the second face; and a first through-hole passing through the board to ventilate at least a part of the region between the board and the semiconductor chip.

Abstract: Metal bond pads are formed over active circuitry in a semiconductor chip in a reliable and cost effective manner. According to an example embodiment of the present invention, a metal bond pad is formed over circuitry in the semiconductor chip. A metal layer is formed over the circuitry and the metal bond pad, and a diffusion barrier layer is formed between the metal layer and the metal bond pad. In this manner, additional metal can be formed on the pad site using only one additional mask step, and thicker metal at the pad site improves the reliability of the chip by providing for a metal cushion at the pad useful in subsequent wire bonding processes.

Abstract: Semiconductor components in a wafer assembly, in which the components are connected to a frame by means of in each case one holder and are formed from the same silicon wafer. The holder connects the respective component to the frame on one side and has a desired breaking point. The desired breaking point is designed as a V-shaped groove, the surfaces of which form crystal planes. According to the method, the patterning for production of the holder takes place on the wafer back surface, with subsequent wet chemical anisotropic etching of the V-groove. In this way, the holder is produced independently of the processing of the wafer front surface, and when the semiconductor component is removed a defined broken edge is formed without there being any risk of the semiconductor component being damaged.

Abstract: A configuration of fuses in a semiconductor structure having Cu metallization planes is provided. The semiconductor structure has an Al metal layer on the topmost interconnect plane for providing Al bonding pads. The fuses are configured as Al fuses and, in the semiconductor structure having Cu metallization planes, are provided above the diffusion barrier of the topmost Cu metallization plane but below a passivation layer.

Abstract: A method for designing an input output cell of an integrated circuit. The input output cell has a required area, a width, and a height. The bonding pad pitch length between adjacent bonding pads of the integrated circuit is measured. The width of the input output cell is specified to be substantially equal to the bonding pad pitch length. The required area is divided by the width to determine a first value, and the height of the input output cell is specified to be substantially equal to the first value. In this manner, the width of the input output cells is no greater than the distance between two adjacent bonding pads, and thus the input output cells can be placed very close together, facilitating their use in input output limited integrated circuit designs. However, the height of the input output cells is no greater than is necessary to enclose the required area of the input output cell, thus facilitating their use in core limited integrated circuit designs.

Abstract: High performance (surface channel) CMOS devices with a mid-gap work function metal gate are disclosed wherein an epitaxial layer is used for a threshold voltage Vt adjust/decrease for the PFET area, for large Vt reductions (˜500 mV), as are required by CMOS devices with a mid-gap metal gate. The present invention provides counter doping using an in situ B doped epitaxial layer or a B and C co-doped epitaxial layer, wherein the C co-doping provides an additional degree of freedom to reduce the diffusion of B (also during subsequent activation thermal cycles) to maintain a shallow B profile, which is critical to provide a surface channel CMOS device with a mid-gap metal gate while maintaining good short channel effects. The B diffusion profiles are satisfactorily shallow, sharp and have a high B concentration for devices with mid-gap metal gates, to provide and maintain a thin, highly doped B layer under the gate oxide.

Abstract: A new multilayer dielectric film for improving dielectric constant and thermal stability of gate dielectrics is provided. The multilayer dielectric film comprises a first layer formed of a metal oxide material having a high dielectric constant, and a second layer formed on the first layer. The second layer is formed of a metal silicate material having a dielectric constant lower than the dielectric constant of the first layer. A semiconductor transistor incorporating the multilayer dielectric film is also provided.

Abstract: The invention relates to a process of forming a compact bipolar junction transistor (BJT) that includes forming a self-aligned collector tap adjacent the emitter stack and an isolation structure. A base layer is formed from epitaxial silicon that is disposed in the substrate.

Abstract: A self-aligned vertical transistor DRAM structure comprising a self-aligned trench structure and a self-aligned common-drain structure are disclosed by the present invention, in which the self-aligned trench structure comprises a deep-trench capacitor region having a vertical transistor and a second-type shallow-trench-isolation region being defined by a spacer technique and the self-aligned common-drain structure comprises a common-drain region being defined by another spacer technique. The self-aligned vertical transistor DRAM structure is used to implement two contactless DRAM arrays. A first-type contactless DRAM array comprises a plurality of metal bit-lines integrated with planarized common-drain conductive islands and a plurality of highly conductive word-lines. A second-type contactless DRAM array comprises a plurality of metal word-lines integrated with planarized common-gate conductive islands and a plurality of common-drain conductive bit-lines.

Abstract: A multi-chip module has at least two semiconductor chips. Each of the semiconductor chips has chip electrodes of the semiconductor chip, electrically conductive interconnections for electrically connection with the chip electrodes, electrically conductive lands for electrically connection with the interconnections, external terminals placed on the lands, and a stress-relaxation layer intervening between the lands and the semiconductor chip. The semiconductor chips are placed on a mounting board via the external terminals. The stress-relaxation layer of a first semiconductor chip is thicker than the stress-relaxation layer of a second semiconductor chip having a distance from a center thereof to an external terminal positioned at an outermost end portion thereof smaller than that of the first semiconductor chip.

Abstract: The present invention discloses a semiconductor memory device having a bit line and a metal contact stud, wherein the metal contact stud is formed on a different layer from a layer on which the bit lines are formed.

Abstract: A parallel-plate, voltage-variable capacitor is designed to have an increased current conducting perimeter relative to its area. In one approach, the perimeter is increased by changing the shape of the plates. In another approach, the varactor is implemented by a number of disjoint plates, which are coupled in parallel.

Abstract: The invention relates to the protection of devices in a monolithic chip fabricated from an epitaxial wafer, such as a wafer for a Group III-V compound semiconductor or a wafer for a Group IV compound semiconductor. Devices fabricated from Group III-V compound semiconductors offer higher speed and better isolation than comparable devices from silicon semiconductors. Semiconductor devices can be permanently damaged when exposed to an undesired voltage transient such as electrostatic discharge (ESD). However, conventional techniques developed for silicon devices are not compatible with processing techniques for Group III-V compound semiconductors, such as gallium arsenide (GaAs). Embodiments of the invention advantageously include transient voltage protection circuits that are relatively efficiently and reliably manufactured to protect sensitive devices from undesired voltage transients.