Abstract: A method and apparatus for ensuring the communication of a minimal length data stream in a system including a host and a storage management device is provided. The method and apparatus includes first and second buffers for simultaneously receiving compressed data and the original data from the host. The system compares the length of the data in the first and second buffers. If the data has expanded, indicating that compressed data is longer than the original data, the original data is provided to the storage media. If the data has not expanded, indicating that the original data is longer than the compressed data, then the compressed data is provided to the storage media.

Abstract: A computer comprising a main body, a connector having pins for connecting an external display to the main body, a register for storing data representing a first status or a second status in accordance with the voltage of specified ones of the pins of said connector means, and a display controller for controlling the external display. The computer further comprises a data-reading section for repeatedly reading the data stored in the register and counting the number of times the data representing the first status is read from said register means, and detecting section for determining that the external display is connected to the connector when the number of times the data representing the first status is read from the register reaches a prescribed value.

Abstract: Method and means are provided for simulating a contiguous data space within a computer memory, and for placing and accessing data objects of various sizes within the simulated contiguous data space. Multiple, sub-data spaces are concatenated in such a way that each page and each sub-data space in the contiguous data space are uniquely identified. Data objects are placed in the contiguous data space and at the first reference to a page of the data object, only the segment containing the referenced page in the contiguous data space is mapped to the database storage disk. Once a data space page is mapped, the operating system can read the page into memory without requesting a disk operation from the database manager. On modifying a page, if the database disk page location is changed, the contiguous data space page is remapped without changing the page address in the data space.

Abstract: A memory control apparatus that compresses the time widths of time slots of addresses sequentially outputted from a data processing unit so as to access a memory. Readout data is transferred to the data processing unit while expanding the time slot. In a vacant time formed by compressing the time widths of the time slots of the addresses from the data processing unit, refresh processing or hard disk transfer processing is executed. The time widths of the time slots of addresses sequentially outputted from a CPU are compressed so as to write data in the memory, and parallel to this operation, refresh processing can be executed in a vacant time. The memory control apparatus is suitably used in accesses of waveform data between a tone generator system and a waveform memory. Waveform data supplied from another unit can be written in the waveform memory parallel to tone generation using all tone generation channels of the tone generator system for tone generation.

Abstract: A Motion Picture Experts Group (MPEG) multiplexed data bitstream includes encoded video and audio data units, which are prefixed with headers including Presentation Time Stamps (PTS) indicating desired presentation times for the respective data units. The data units are decoded, and presented at a fixed time after decoding, such that the fixed time can be subtracted from the PTS to provide a desired decoding time. The bitstream is parsed, the video and audio headers are stored in video and audio header memories, and the associated video and audio data units are stored in video and audio channel memories respectively. A first interrupt is generated each time a header is stored, and a host microcontroller responds by storing the PTS from the header and the starting address of the corresponding data unit in the channel memory as an entry in a list.

Abstract: A method and apparatus for executing floating-point instruction pairs in a pipelined manner in which exceptions are predicted during an execution stage. In response to a possible exception, the execution pipeline can stall the pipeline. The floating-point pipeline and the integer pipelines are stalled in an execution stage and a decoding stage, respectively. Once stalled, the floating-point microinstructions are executed, the state of the machine is updated and then any exceptions are reported.

Abstract: A decoder that includes a micro-alias register to store information from a micro-operation for use by later micro-operations in the micro-operation flow. The decoder includes one or more XLAT PLAs that produces PLA control micro-operations ("Cuops"), a microcode sequencing unit that produces microcode Cuops, and an aliasing mechanism that extracts fields and stores them in macro-alias registers. A multiplexer is provided to select the appropriate Cuop to be stored in a Cuop register. Multiple Cuops may issue each cycle. A multiplexer is coupled to select one of the Cuops and to store predetermined fields in the micro-alias register for use by subsequent Cuops. Micro-alias data and macro-alias data can be utilized simultaneously with a Cuop to form an Auop.

Abstract: A structured database system includes a first unit for obtaining a structure definition frame of a document showing a structure of the document, and a second unit for storing body data of the document in a database together with the structure definition frame.

Abstract: Customer Premise Devices (CPDs) and associated methods according to the invention allow subscribers to send diverse subscriber requests and to receive incoming information such as movies, videogames, educational, business and consumer information, and scientific and other reasearch-related database information. The CPD controls transmissions, carried over a communications medium, between a central information source and customer premise equipment, such as TVs and computers, housed at a remote station. The CPD has (a) a first interface linked to the communications medium; (b) a second interface linked to the customer premise equipment; and (c) an interface controller linking the first interface and the second interface.

Abstract: A software compiler having a code generator and a scheduler. The code generator transforms a lowered intermediate representation (IR) of a source computer program, written in a known computer language, to an assembly language program written in a non-standard instruction set. In particular, the code generator translates vector instructions in the lowered IR to vector instructions from the non-standard instruction set. The vector instructions from the non-standard instruction set are defined such that assembly language programs written with them do not suffer from the effects of pipeline delays. Therefore, according to the present invention, the code generator eliminates the effects of pipeline delays when transforming the lowered IR to the assembly language program. Since the code generator eliminates the effects of pipeline delay, the scheduler's task is greatly simplified since the scheduler need only maximize the use of the functional units.

Abstract: Apparatus and methods for specifying contexts for machine-executable instructions. Modern graphical user interface systems employ the callback programming style. In this style, a system event handler responds to an event by executing application-level callback code and providing event information concerning the event as part of the context of the execution. The technique disclosed herein uses callback information names to specify the relationship between the event information and the execution context. The callback information names are defined globally, but represent the event information for a single execution of the callback code. Using the callback information names, it is possible to define the callback code in the function which adds the callback code to the graphical user interface system.

Abstract: Control is executed in such a manner that storage and forward exchange can be performed even when a communication message comprising media information sent from a communication terminal exceeds a predetermined message length, thus improving the utilization efficiency of the system as a whole. Specifically, when a mailbox registration request message addressed to one terminal is received by a mail processing apparatus through a communication controller upon having been sent from another terminal via a network, a main controller determines whether the received message exceeds a predetermined maximum message length. If it does, then it is determined if a media classification is indicative of image information. In case of image information, it is determined by a media table whether the terminal for which the message is destined is capable of receiving the image information.

Abstract: A method is provided which controls a data processing system having two common memories forming a duplex memory, a plurality of clusters provided in common for the common memories, and input/output paths connecting the clusters to the common memories. The method includes the steps of detecting a failure which has occurred in one of the common memories by each of the clusters, physically disconnecting input/output paths connected to the above-mentioned one of the common memories therefrom when the failure is detected by one of the clusters, and inhibiting the clusters from accessing the above-mentioned one of the common memories in which the failure has occurred. There is also provided a data processing system that uses such a method.

Abstract: A method and apparatus for detecting diskette change is provided. A step pulse signal generated using the CPU is sent to the step pulse line of the disk drive, in addition to the normal step pulse signal which can be issued from the floppy disk controller. Thus, a step pulse can be issued directly by the CPU without using the FDC. By positioning the head in the outmost cylinder and issuing a step pulse, at a time when the direction signal indicates outward direction, the door-open status signal can be updated, without causing movement of the head. By preventing head movement in response to a step pulse, door-open status information is updated without undesirable effects of excessive head movement, drive spinning, head movement noise, constant illumination of the drive light or unnecessarily occupying the CPU or other components.

Abstract: A computer system includes a program executing section for executing a program, an instruction generating section for generating a frequency change instruction in response to the execution of the program, and a changing section for changing the frequency of an operation clock of a system bus in reponse to the frequency change instruction. The frequency of the operation clock of the system bus is changed when an interface having a low operation rate is accessed. Therefore, an average speed of the system can remain high.

Abstract: A macropipelined microprocessor chip adheres to strict read and write ordering by sequentially buffering operands in queues during instruction decode, then removing the operands in order during instruction execution. Any instruction that requires additional access to memory inserts the requests into the queued sequence (in a specifier queue) such that read and write ordering is preserved. A specifier queue synchronization counter captures synchronization points to coordinate memory request operations among the autonomous instruction decode unit, instruction execution unit, and memory sub-system. The synchronization method does not restrict the benefit of overlapped execution in the pipelined. Another feature is treatment of a variable bit field operand type that does not restrict the location of operand data. Instruction execution flows in a pipelined processor having such an operand type are vastly different depending on whether operand data resides in registers or memory.

Abstract: An interconnection topography for microprocessor-based communication nodes consists of opposite arrays of client nodes and resource nodes, with each client node connected to one resource node by a data transfer link, each resource node connected to a resource trunk by a data transfer link, and each node connected to just four neighboring nodes by data transfer links. Communication nodes in the topography are microprocessor controlled, and comprise random access memory and data routing circuitry interfaced to the data transfer links. In one aspect resource nodes are provided with a map of the interconnection topography for use in routing data. In another aspect, individual ones of the communication nodes are programmed as servers for receiving client requests and scheduling routing of resource data.

Abstract: A vector data processing apparatus having a set of vector registers, one or more memory access pipelines, and one or more composite calculation pipelines, wherein the vector registers consist of a plurality of banks, and each bank is independently accessible. Each of the pipelines can cyclically access each of the banks of the vector registers when one or more of a predetermined number of time slots, through each of which time slots the access is carried out, are assigned to an instruction using the pipeline. Immediately when a memory access instruction is received, a vector unit control circuit, which controls operations of the vector data processing apparatus, assigns a time slot for a newly-detected memory access instruction using a memory access pipeline, if it is determined that the memory access pipeline is available based on the pipeline operation status flags, and that the time slot is available based on the detected status of the predetermined number of time slots.

Abstract: During execution, API calls to the operating system in a master processor are transferred to slave processors by an event redirection mechanism, the API calls are then provided to the operating systems of the slave processors by their event redirection mechanisms, such that the same screen or window appears at both the master processor and slave processors. Messages generated at the slave processors are likewise provided to the message queue of the master processor by the event redirection mechanism, and then provided to the application running on the master processor. Therefore the slave processors share the application of the master processor.

Abstract: The disclosed data processor (10) has a future file (60) for providing the most recent value of a set of architectural registers (32, 36) to the various execution units (20, 22, 24, 26, 28, 30) of the data processor. The most recent value of the set of architectural registers is determined with respect to the original instruction sequence. The future file provides a single source for operand look-up at instruction dispatch and can be corrected in a single cycle in the event of an exception condition.