Abstract: Logic examines signals from an instruction fetch unit to determine if the next instruction is a branch. A mux selects one of the 4 instruction words. MACRO [0:3] and a displacement from the selected word. A full adder (40) adds this displacement to the instruction pointer. The result is used as the branch address. The timing is such that a 1 clock lookahead is sufficient to hide this calculation from program execution. The branch register address is determined by the process ID and the macro mode state bit. The branch by pass mechanism causes the branch address to be driven from the calculation instead of a branch register. If a branch fail or scoreboard hit occurs, a write cancellation is generated to stop the current address calculation from being stored in a branch register. If a branch fail or scoreboard hit does not occur, then the current address calculation is stored in a branch register. If a branch bypass occurs, then the branch address is driven from the calculation.

Abstract: A program generating method for automatically generating a program used in a simulation of a physical phenomenon by using computers, wherein inputted information such as the shape of a domain where the physical phenomenon such as that in a fluid takes place, mesh division information therefor, a partial differential equation dominantly representing the physical phenomenon and boundary conditions thereof are inputted, differential operators included in the inputted partial differential equation and an equation representing the boundary condition are expanded to generate discrete equations and the generated discrete equations are coded to automatically generate simulation programs.

Abstract: In a computer system, a plurality of commands selected by an operator are sequentially inputted to specify respective processing to be executed and respective data to be used in the processing. Each of the inputted commands is executed before an input of a command subsequent thereto to output data resultant from an execution of the command. In the input operation, several commands are supplied to specify, as data to be respectively used by the plural commands, resultant data attained by the execution of commands inputted prior thereto. From the plural input commands are extracted a series of several commands employed to generate at least one resultant data associated with the plural commands and selected by the operator. Based on the extracted command series, there is generated a program executing processing to be achieved by the command series or processing equivalent thereto.

Abstract: An interconnect interface for connecting a host computer to an interconnect fabric in a multi-computer data processing system including a plurality of host computers. A sending process having permission to send messages to a receiving process on another computer in the system controls a portion of the computer memory on the computer running the receiving process. The location of the memory in question together with a protection key value are stored in a table in the receiving terminus of the interconnect interface on the recipient. The sending terminus of the interconnect interface on the computer running the sending process incorporates information in each message packet which specifies an entry in this table. Each message also includes a protection key that must match the corresponding entry in the table on the receiving terminus.

Abstract: An operator of a digital computer system enters application call commands to execute a series of application programs. The execution of the application programs is affected by application operational commands, and involves the import and export of data among the application programs. The data are imported and exported through objects such as files. The computer system includes a core executive program that records a script of the application call commands. The application programs each include a client executive routine that records the application program's operational commands together with import and export information, and transmits the operational commands and the import and export information to the core executive program before termination of the application program. The core executive program integrates the operational commands into the script, and displays a graphical picture of the state of the computer system.

Abstract: A method and mechanism for suspending and resuming a keyboard controller. The present invention includes a method and mechanism for saving the state of an input device, such as a keyboard and/or mouse, such that the power to those devices may be removed. The keyboard controller of the present invention is capable of performing a password security function. The present invention allows the keyboard controller to be suspended and resumed without jeopardizing the password security function.

Abstract: A logic simulator is distributed over a plurality of processing nodes for simulating a circuit. A plurality of logic simulation programs execute on respective ones of the nodes, and simulate respective parts of the circuit. Each of the logic simulation programs executes at its own pace, and either receives an input from or supplies an output to another of the nodes. Each of the logic simulation programs also predicts an input when unavailable from another of the nodes. A host broadcasts a breakpoint time to all of the nodes. A plurality of logic simulation controllers execute on respective ones of the nodes, and direct storage of nets and/or states of the logic simulation programs. Each of the logic simulation controllers receives the breakpoint time from the host and reports to the host when the respective logic simulation program has advanced to or past the breakpoint time.

Abstract: The present invention comprises a decoding system for decoding a data accessing instruction for accessing data stored in a plurality of registers wherein the registers are of different types including a global type, a local type, an input type and an output type, the registers being cataloged into a plurality of windows arranged in a predefined window sequence wherein each window including a plurality of registers of each of the types arranged in a predefined register sequence wherein the output registers of one of the windows being overlapping with the input registers of an adjacent window which being next in sequence of the window sequence. The decoding system comprises an instruction issuing means for issuing a data accessing instruction including a plurality of bits wherein the bits being encoded in an order corresponding to the window sequence and the register sequence and a set of bits of the instruction is used for defining a corresponding window and a corresponding type of the registers.

Abstract: A memory management unit suitable fo use in a digital signal processor having internal and eternal memories is described. The unit is especially designed to facilitate numeric algorithms such as fast fourier transforms, auto-correlation and digital filtering by relieving the programmer from the need to monitor memory accesses. Automatic post-updating of memory addresses is provided after indirect memory references. Also, memory boundary-checking is performed according to a user-specified modulus value, and a memory reference is automatically adjusted to fall within the user-specified address range. A dual-access register file stores initial memory addresses and their associated modulus values and in a dual-bus embodiment a pair of address generation units provides post-updates of the addresses stored in the register files.

Abstract: A configurable emulator system for emulating a microcontroller device architecture selected from a plurality of microcontroller device architectures is provided. The configurable emulator includes a master microcontroller emulator comprising at least one functional block that responds to a mode select input signal for designating the functional block as having a desired integrated circuit feature. The master microcontroller emulator includes means responsive to control code for executing the control code. A configuration mode selector responds to an external input signal by asserting a configuration flag. Bus selector means responds to the assertion of the configuration flag by transferring configuration data provided at a bus selector input to a configuration data output. The bus selector transfers control code provided at the bus selector input to the master microcontroller emulator via a control code output when the configuration flag is not asserted.

Abstract: A slip producing apparatus and method for producing a slip having a variable number of word names and respectively corresponding word data, wherein a plurality of slip types and a variable arbitrary number of word names corresponding to each slip type are stored in advance in a word name storage device; an input device is provided for inputting data designating the slip type and for sequentially inputting word data respectively corresponding to the variable number of word names of the designated slip type; and the inputted word data is stored in a word data storage device.

Abstract: The present invention relates to a system including a terminal connected by a transmission line to a central processing unit, the terminal including a memory divided into a program memory and a working memory of the RAM type, the program memory in turn including a volatile memory, a safeguarded memory of the EEPROM type or RAM type with batteries, and a resident memory of the ROM or PROM type, characterized in that each of the memories comprising the program memory is divided into a noncertified zone, the terminal including an interpreter program for interpreting between a program written in a high-level universal compact language and the language specific to the microprocessor of the terminal, this interpreter program being capable of access to each of the memory divisions, and a remote loading monitoring program including at least one instruction CHSB, the command word of which is stored in one of the registers and expresses the remote loading possibilities of the various zones.

Abstract: A document data input system for a scanner capable of storing scanner data to another buffer memory of a microprocessor when applying the scanned data to a host computer. The document data input system comprises a host computer for storing scanned data to its internal hard disk, a scanner for scanning the document data, a scanner interface unit for interfacing between the host computer and the scanner, a microprocessor associated with a global memory and a local memory, and an interface unit for latching the data from the scanner interface unit and applying the data to the microprocessor, and applying a completion signal to the scanner interface unit when the data input to the microprocessor is completed.

Abstract: A microprogram control system has first and second microprogram control units and first and second arithmetic circuits corresponding to the first and second microprogram control units, respectively. The first unit has a first control memory holding microinstructions for controlling the first arithmetic circuit and a first condition register for storing status information given as a branch condition from the first arithmetic circuit. The second unit is made up of corresponding structure. In response to a start microinstruction read out from the first control memory, the first unit stores a start command and a start address in the start microinstruction into a command register and a start address register therein, respectively, and sends the start command, the start address and the status information to the second control unit.

Abstract: The emulator includes first and second pipelined stages connected through a bidirectional bus for executing source instructions normally executed by a different/source computer in a highly overlapped manner. The first stage includes an emulator chip which performs the function of fetching and decoding each source instruction stored in cache memory resulting in the generation of a number of vector addresses required for executing the instruction by the second stage. The second stage includes a high performance microprocessor chip having on-chip instruction and data caches for storing a plurality of emulation subroutines and data fetched during subroutine execution. In pipelined fashion, the emulator chip fetches and decodes each source instruction which generates a vector branch address which is loaded into the branch vector register while the microprocessor chip fetches and executes emulation subroutines specified by the vector address transferred via the bus for each previously decoded source instruction.

Abstract: Disclosed is a method for simulating an operation of an event driven logic circuit in response to changes of the signal status of each terminal of all the elements in the logical circuit, based on event data each containing event time indicating when the signal status has changed, status change indicating how the status has changed, an element identifier identifying the element, and a terminal identifier identifying the terminal, the method comprising a simulation time output step for outputting data indicating simulation time which is continuously counted up; a first selection step for selecting the event data whose event time is equal to the simulation time; a second selection step for selecting the event data whose event time is earliest among event data present for all the input terminals of the element corresponding to the event data; a simulation step for generating new event data depending on a change of the signal status of the output terminal of the element corresponding to the event data, based on t

Abstract: A high speed three-to-one data dependency collapsing ALU can be used to support multiple issue of instructions. The computing apparatus supports multiple issue of instructions it is useful in CISC, superscalar, superscalar RISC, etc. type computer designs. The concept of the ALU is presented along with a detailed description of a design. The apparatus allows the execution of any combination of two independent or dependent arithmetic or logical instructions in a single machine cycle. The 3-1 collapsing ALU structure has a 3-2 carry save adder (CSA); and a 2-1 control arithmetic logic unit (CALU) coupled for an input from the carry save adder; and a first pre-adder logic block coupled with an output to the control arithmentic logic unit; and a control generator; and a second controlled logic block coupled to receive an input from said control generator and having its output coupled to said control arithmetic logic unit.

Abstract: A method of handling a fault associated with a first floating point instruction upon reaching the next sequential floating point instruction is described. The first floating point instruction is decoded. A first floating point microinstruction received from a control memory is stored in a first latching means and in a second latching means. The next sequential floating point instruction is decoded. There is a jump to a plurality of exception handler microinstructions stored in the control memory, the jump occurring upon the detection of the fault associated with first floating point instruction. The plurality of exception handler microinstrictions includes an exception handler floating point microinstruction. The exception handler floating point microinstruction received from the control memory is stored in the first latching means, replacing the previous microinstruction stored in the first latching means.

Abstract: A pipelined processing system in which context switching for each of the pipelined processing circuits within the pipeline may be accomplished without flushing the data from the pipeline. This is accomplished by sending the pipeline commands and data together through the pipeline and differentiating the commands from the data using a flag added to the commands and data which specifies whether the associated data word is a command or data. During operation of the pipeline, when the input data is received by one of the pipelined processing circuits in the pipeline, the flag is checked to see if the associated data word includes a command. If the associated data word includes data to be processed, it is processed in accordance with the current configuration of the pipeline.

Abstract: A pulse generating device according to the present invention is operated in accordance with a pulse control command including output time data about output pulse given from external equipment such as a CPU. The pulse control command including the output time data about the output pulses is transferred to a master memory of a contents addressable memory at an optional timing from outside. The contents of that master memory are copied to a slave memory in response to copy enable signals transmitted from a copy enable device. The copy enable signals are transmitted whenever a predetermined number synchronizing signals showing an end of the pulse period are generated from the interval timer. The contents addressable memory reads out the output control command of the output pulse from a slave memory when the timer value of the interval timer coincides with the time data of the slave memory. The output control circuit transmits output pulses which correspond to the control command read out as described above.