Abstract: A method and apparatus is provided for integrating a logic level simulation with an instruction level simulation for more accurate and faster system level simulation for testing. A host system or processors (CPU) is simulated by the instruction level simulator and the simulation of an input/output subsystem is modeled by the logic level simulator. The two simulations work side by side communicating through an interprocess communication (IPC) device and both simulations can perform a read/write access. Hence, a DMA and a slave access can occur at the same time causing a deadlock situation where both simulators are waiting for data and acknowledgment from each other at the same time. An input/output subsystem SBus module resolves this deadlock by deferring the non-DMA transaction. Finally, the synchronization of the two simulations is handled by the invention allowing the two simulators to run as asynchronous peers.

Abstract: In a data exchange network, in which various resources, such as hubs, routers, etc., distributed across the data exchange network are remotely controlled from a single point of maintenance, a consistent approach is provided for managing the network hardware resources. A set of consistent displays is provided for remote front panels allowing visual management of remote, heterogeneous devices, while also allowing the display of nongraphical data in a usable form.A common user interface allows operator control of the network, which may include many disparate types of equipment, supplied by various manufacturers. User definition of each network element is allowed based on a uniform vocabulary of element representations. A network management architecture provides a common development language for describing specific functions and attributes of network elements. Each element includes a protocol module which, in conjunction with a system engine, effects coordinated network control.

Abstract: A processing unit couples to a system bus in common with a peer processor, a main memory, in addition to other units, and includes a microprocessor which tightly couples to a local memory also accessible from such bus. The processing unit also includes an addressable electrically erasable programmable read only memory (EEPROM) unit which is coupled to the microprocessor and the system bus. The EEPROM unit stores in first and second separate regions, both of which occupy the same address space normally allocated for storing the microprocessor's boot code, on-board diagnostic (OBD) routines and operating system boot routines, respectively. EEPROM control circuits at power-up, condition the EEPROM unit to address the first region for executing OBD routines to verify that the processing unit is operating properly, including the ability to properly issue commands to units connected to the system bus.

Abstract: Method and system for locating nomadic users in a personal communication services (PCS) system by utilizing two strategies for locating such users and a per-user criterion for determining which, if any, of the two strategies should be used. The method and system augment basic two-level strategies for locating users specified in IS-41 and GSM standards of PCS systems. One strategy utilizes forwarding pointers and the other strategy utilizes per-user location caching. One per-user criterion is a call-to-mobility ratio (CMR) which is the ratio of the average rate at which a user receives calls to the average rate at which the user moves. A variation of this criterion is the local CMR (LCMR) which is the ratio of the average rate at which a user receives calls from a given registration area, to the average rate at which the user moves. The method and system reduce the average time and overhead required to locate and deliver information to such nomadic users.

Abstract: A logic simulator for optimal configurability of combinatorial and sequential logic circuits in a simulated behavioral form. The present invention contains process oriented functional blocks with event posting to eliminate unnecessary evaluations in logic simulation. Also, the present invention manages a process to logic signal(s) and logic signal to process(s) sensitivity relationship(s) which reduces the traditional overhead of event scheduling and stabilization. The processing logic of the preferred embodiment is operably disposed within the random access memory and executed by the processor of a computer system. Upon activation of the present invention and initialization of all signals, a test is performed to determine if the logic network being simulated is in a stable condition. If the logic network is not stable, a loop is initiated for propagating signals and updating signal states throughout the logic network.

Abstract: A communication system for exchanging information between a remote terminal and a host terminal over a signalling channel of an ISDN network which does not need to establish communication over voice or data channels of the ISDN is disclosed. The communication system transmits credit transactions such as authorization requests from a remote terminal to a host computer, processes such transactions, and transmits a response back to the terminal, in which all such communication is performed over a signalling channel of ISDN. Preferably, the authorization request as well as the response from the host includes a "user-user information element" and are formatted in accordance with the CCITT Q.931 standard.

Abstract: A data processing machine comprises a plurality of elementary machines (SUPMS, DEP, ARR, . . . ) disposed in a plurality of levels (level 1, level 2, . . .), and an event presentation device (PTA) responding to the arrival of an event by identifying the lowest machine level that is active and by identifying the elementary machine that is active in this lowest active machine level to present the event to said active elementary machine.

Abstract: Transmit and receive data are stored in buffer regions defined in first and second memories of a system residing on a network. The buffer regions are pointed to by multiple descriptor rings that are also stored in the memories. In accordance with one aspect of the invention, the two memories reside on separate busses connected to a common buss containing a processor. The processor communicates with one or the other of the memories using a handshaking protocol. In accordance with another aspect of the invention, receive data incoming to the system is scattered among multiple descriptor rings. A further aspect splits a frame among multiple descriptors depending on a characteristic code carried by the frame, e.g., in a frame control field. The size of the first descriptor, smaller than that of the others, is programmed to correspond to the size of the header of each frame. Synchronization between headers and data of a frame is maintained by a frame number stored in each descriptor.

Abstract: A co-processor works in conjunction with a primary processor which does not natively support co-processing. In a memory which provides instructions for the primary processor, parameters for use by the co-processor are embedded within the instructions. This is done by placing the parameters in fields which are unused by the primary processor. When the primary processor accesses the local memory, the addresses generated by the primary processor are monitored by the co-processor. When the co-processor detects a pre-determined combination within an address generated by the primary processor, the co-processor accesses the data sent from the local memory to the primary processor. The co-processor then extracts the parameters embedded within the unused fields of the accessed data.

Abstract: An object oriented distributed computing system is provided. Processing means call a location service within automatically generated stubs in response to a request for a service provided by a particular object. The location service is automatically called on behalf of the requester to locate the target object when the request is issued. Multiple Object Managers reflecting multiple Object Models are permitted in the system. Programmers and users do not need to know the Object Model adhered to by an Object Manager. A request to any object in the system is independent of the Object Model of the sought object's Object Manager. A generic interface enables new Object Managers reflecting new Object Models to be easily added to the system. Availability of the target object is independent of association of the target object with a process at the time the request was issued. Deactivation of processes is automatically accomplished in response to the system needing resources.

Abstract: A digital computer system capable of processing two or more computer instructions in parallel and having a cache storage unit for temporarily storing machine-level computer instructions in their journey from a higher-level storage unit of the computer system to the functional units which process the instructions. The computer system includes an instruction compounding unit located intermediate to the higher-level storage unit and the cache storage unit for analyzing the instructions and adding to each instruction a tag field which indicates whether or not that instruction may be processed in parallel with one or more neighboring instructions in the instruction stream. These tagged instructions are then stored in the cache unit. The computer system further includes a plurality of functional instruction processing units which operate in parallel with one another. The instructions supplied to these functional units are obtained from the cache storage unit.

Abstract: A method and apparatus for generating control signals for a high speed First In First Out (FIFO) buffer. Moreover, the present invention limits the instances where signal glitches may occur. A first pair of circular shift registers are used to control writing data to and reading data from the FIFO. The outputs of each register in each shift register are coupled to enable individual read and write lines of a FIFO memory device. A single logical one value circulates through the shift registers to indicate a FIFO location where data may be written to or from. Toggle latches are coupled to each shift register. The values in the toggle registers change responsive to a read or write operation. By comparing the logical one values in the corresponding positions in the shift registers, and considering the values from the toggle latches, EMPTY and FULL conditions are detected.

Abstract: According to this invention, when a program requiring an inseparable operation is to be executed, prior to its program processing, an instruction fetch counter setting instruction is executed by an instruction fetch counter setting unit, and a value indicated by the instruction fetch counter setting instruction, i.e., an instruction count required for the program processing, is set in an instruction fetch counter. The instruction fetch counter is counted down by a count down unit every time an instruction is fetched. When an interrupt is generated, an interrupt control unit refers to the instruction fetch counter. When the reference value is "1" or more, the interrupt is inhibited until the value is set to be "0.

Abstract: A computer comprising a main body, a connector having pins for connecting an external display to the main body, a register for storing data representing a first status or a second status in accordance with the voltage of specified ones of the pins of said connector means, and a display controller for controlling the external display. The computer further comprises a data-reading section for repeatedly reading the data stored in the register and counting the number of times the data representing the first status is read from said register means, and detecting section for determining that the external display is connected to the connector when the number of times the data representing the first status is read from the register reaches a prescribed value.

Abstract: An extremely fast and efficient Linker for a Magnetic Resonance Imaging (MRI) system Nuclear Magnetic Resonance (NMR) pulse control sequencer efficiently derives subsequent blocks of microcode to be loaded by using the contents of a memory buffer containing previously loaded microcode as a template, Most of the template is reused "as is". Only the relatively few field values in the microinstructions which change from one signal generation process, or cycle, to the next are replaced with new values. Offsets are tabulated of instructions which have associated multi-entry cycle indexed program change table (PCT) values. When further code is to be linked and loaded, the linker accesses the PCTs based on the table and to inserts new values into the appropriate instruction fields. The microcode memory image may be continuously maintained in a host memory buffer and re-edited successive times.

Abstract: A computing system has multiple instruction pipelines, wherein one or more pipelines require translating virtual addresses to real addresses. A TLB is provided for each pipeline requiring address translation services, and an adress translator is provided for each such pipeline for translating a virtual address recieved from its associated pipeline into corresponding real addresses. Each address translator comprises a translation buffer accessing circuit for accessing the TLB, a translation indicating circuit for indicating whether translation data for the virtual address is stored in the translation buffer, and an update control circuit for activating the direct address translation circuit when the translation data for the virtual address is not stored in the TLB. The update control circuit also stores the translation data retrieved from the main memory into the TLB.

Abstract: An instruction buffer controller according to the present invention comprises an instruction buffer for prefetching and writing of instructions in the main storage and a storage pointer which holds the address of the instruction fetched from the instruction buffer currently being executed or initial addresses of completed instructions in the instruction buffer. It also comprises a storage controller which stores the instruction currently being executed at the instruction buffer until execution completion of that instruction or stores a predetermined number of completed instructions at the instruction buffer. It causes its judgment means to judge whether the address of the instruction to be re-fetched exists between the writing address for the instruction buffer and the storage pointer address and, if such address exists there, sets the address of the re-fetched instruction at the reading pointer as the reading address of the instruction buffer.

Abstract: A method for improving SCSI controller operations by actively patching SCSI processor instructions. In a first case, tag values assigned to queues for tagged queue operation are a multiple of the SCSI processor jump instruction length. When reselected, the tag value is patched or overwritten as the least significant byte of the address of a jump instruction. The upper bytes point to the beginning of a jump table. Each entry in the jump table is a jump instruction to the sequence for a particular queue or thread. Thus simple entry is made to the desired thread without a conditional branch tree. In a second case, special SCSI operations are directly handled by the host device driver and the SCSI processor only performs conventional data transfers and similar operations. The device driver patches the message length of the SCSI processor code to an illegal value, so that an illegal instruction develops, prompting the host device driver to perform the operation at a register level.

Abstract: A simulator system of a digital network which may contain a memory. The system includes at least three hierarchical data storage buffers 18, 20, 24, 26 for storing the simulated network signals for simulated registers and combinatorial logic at the close of each simulation cycle. Each buffer 20, 24, 26 has a plurality of entries comprising a periodic sampling, sometimes referred to as checkpointing, of the next lower storage buffer. The system also includes a change management list 30 and a memory data array 32 for respectively storing time/address pairs and time/value pairs to identify the time, address and value of memory writes. These pairs of data are updated (i.e., checkpointed) each time a selected data storage buffer 24, 26 starts to have previously written locations overwritten by newer data.

Abstract: An address of a branch instruction, a branch target address thereof, and a type thereof are stored as branch history information in a branch instruction buffer. In addition, a return address for a return from a subroutine is retained in a return buffer. A look-up operation is conducted through the buffer by using the pre-fetch address such that when a hit occurs, a branch target address is output from the buffer depending on a branch instruction type. Consequently, the branch processing is achieved at a high speed. Particularly, the processing speed of an unconditional branch instruction containing a return instruction is increased.