Patents Examined by Kenneth B. Wells
  • Patent number: 11962294
    Abstract: A method for driving an output node includes driving a control node of an output device coupled to the output node according to an input signal and using a fixed regulated voltage and a variable regulated voltage. The method includes generating the fixed regulated voltage based on a first power supply voltage, a second power supply voltage, and a first reference voltage. The method includes generating the variable regulated voltage based on the first power supply voltage, the second power supply voltage, and a second reference voltage. The method includes generating the second reference voltage based on the first power supply voltage, the second power supply voltage, a reference current, and a predetermined target voltage level of the control node of the output device. In an embodiment of the method, generating the second reference voltage includes periodically calibrating the second reference voltage.
    Type: Grant
    Filed: November 14, 2022
    Date of Patent: April 16, 2024
    Assignee: Skyworks Solutions, Inc.
    Inventors: Peter Onody, Tamas Marozsak
  • Patent number: 11955961
    Abstract: Disclosed is a switch circuit for an ultra-high frequency band, which includes a transistor including a first terminal connected to an input stage, a second terminal connected to an output stage, and a gate terminal, an inductor connected to the transistor in parallel, between the input stage and the output stage, a variable gate driver to apply a gate input voltage to the gate terminal and, an input resistor connected between the variable gate driver and the gate terminal. The variable gate driver adjusts the gate input voltage to be in one of a first voltage level for turning on the transistor and a second voltage level for turning off the transistor. The second voltage level varies depending on a capacitance between the first terminal and the second terminal, when the transistor is in a turn-off state.
    Type: Grant
    Filed: August 2, 2022
    Date of Patent: April 9, 2024
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Hong Gu Ji, Dong Min Kang, Byoung-Gue Min, Jongmin Lee, Kyu Jun Cho
  • Patent number: 11949411
    Abstract: A semiconductor device (1) according to the present disclosure includes: an n-channel depletion-mode transistor (10); an input matching circuit inside which the gate terminal (11) and the ground terminal (22) are DC-connected; a self-bias circuit (26) including a resistor (14) biasing the transistor (10) by a voltage drop due to a current flowing through the resistor (14), and a capacitor (15) connected in parallel to the resistor 14) and regarded as short-circuit at a frequency of the high-frequency power; and a diode (31) having an endmost anode connected to the source terminal (12) and an endmost cathode connected to the ground terminal (22), and connected in one stage or connected in series in a plurality of stages in the same direction.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: April 2, 2024
    Assignee: Mitsubishi Electric Corporation
    Inventor: Hitoshi Kurusu
  • Patent number: 11942925
    Abstract: A method for operating a gate driver system includes measuring a first parameter according to a first priority schedule synchronously to a first edge of a switching signal generated by a gate driver integrated circuit and having a variable duty cycle. The method includes after measuring the first parameter of the gate driver system and prior to a second edge of the switching signal, measuring at least a second parameter of the gate driver system according to a first round-robin schedule synchronously to the first edge of the switching signal.
    Type: Grant
    Filed: May 1, 2023
    Date of Patent: March 26, 2024
    Assignee: Skyworks Solutions, Inc.
    Inventors: James Edward Heckroth, Ion Constantin Tesu
  • Patent number: 11940489
    Abstract: A semiconductor device includes: a semiconductor body; an electrical device formed in an active region of the semiconductor body, the active region including an interface between the semiconductor body and an insulating material; and a sensor having a bandwidth tuned to at least part of an energy spectrum of light emitted by carrier recombination at the interface when the electrical device is driven between accumulation and inversion, wherein an intensity of the emitted light is proportional to a density of charge trapping states at the interface, wherein the sensor is configured to output a signal that is proportional to the intensity of the sensed light. Corresponding methods of monitoring and characterizing the semiconductor device and a test apparatus are also described.
    Type: Grant
    Filed: October 15, 2021
    Date of Patent: March 26, 2024
    Assignee: Infineon Technologies AG
    Inventors: Thomas Aichinger, Maximilian Wolfgang Feil, Andre Kabakow, Hans Reisinger
  • Patent number: 11936117
    Abstract: Provided is a dual-band multimode antenna feed for a high-frequency band and a low-frequency band. The feed includes four high-frequency waveguide ports, where each high-frequency waveguide port is connected to a respective high-frequency input/output waveguide. Each high-frequency input/output waveguide includes a high-frequency waveguide aperture facing a first section for mixing electromagnetic modes in the E-plane. The first section is connected to a second section for mixing electromagnetic modes in the H-plane. The feed further includes a low-frequency waveguide port connected to a low-frequency input/output waveguide. A filter is arranged inside the first section to be transparent for plane wave modes exhibited at lower frequencies and reflecting for plane wave modes exhibited at higher frequencies.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: March 19, 2024
    Assignee: SAAB AB
    Inventor: Ola Forslund
  • Patent number: 11936357
    Abstract: An integrated isolator circuit for isolating receiver and transmitter in a Time-Division Duplex transceiver is disclosed. The integrated isolator circuit comprises a first node, a second node and a third node. The integrated isolator circuit further comprises a fist capacitor connected in series with a first switch and connected between the first and second nodes. The integrated isolator circuit further comprises a first inductor connected between the first and second nodes and a second capacitor connected between the second node and the third node. The first switch has an on state and an off state, and the integrated isolator circuit is configured to have a different impedance at a certain operating frequency by controlling the state of the first switch.
    Type: Grant
    Filed: June 14, 2021
    Date of Patent: March 19, 2024
    Assignee: TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
    Inventor: Imad ud Din
  • Patent number: 11936378
    Abstract: An interface circuit and an electronic apparatus, including: a programmable current array (1), generating a first current and a second current transmitted to a common mode and differential mode generation circuit (2) according to an input code, and a third current and a fourth current transmitted to a driving bias generation circuit (3) according to the input code; the common mode and differential mode generation circuit (2), generating a common mode voltage according to the first current, and generating a high level voltage and a low level voltage according to the second current and the common mode voltage; a driving bias generation circuit (3), simulating a load according to the third and fourth currents, and generating a bias voltage based on the load and the low and high level voltages; an output driving circuit (4), converting an input signal into a differential signal in which the common mode voltage and a differential mode amplitude are configurable.
    Type: Grant
    Filed: January 6, 2021
    Date of Patent: March 19, 2024
    Assignees: NO.24 RESEARCH INSTITUTE OF CHINA ELECTRONICS TECHNOLOGY GROUP CORPORATION, Chongqing GigaChip Technology Co., Ltd.
    Inventors: Ting Li, Gangyi Hu, Ruzhang Li, Yong Zhang, Yabo Ni, Dongbing Fu, Jian'an Wang, Guangbing Chen
  • Patent number: 11936367
    Abstract: An acoustic wave resonator is disclosed. The acoustic wave resonator can include a piezoelectric layer, an interdigital transducer electrode positioned over the piezoelectric layer, a temperature compensation layer positioned over the interdigital transducer electrode, and a velocity reduction cover that extends over at least a portion of a central region of the interdigital transducer electrode and over at least a portion of the temperature compensation layer. The velocity reduction cover is arranged to cause a velocity of an acoustic wave generated by the acoustic wave resonator to be reduced.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: March 19, 2024
    Assignee: Skyworks Solutions, Inc.
    Inventors: Hironori Fukuhara, Rei Goto
  • Patent number: 11923832
    Abstract: A gate driver system includes a transistor configured to be driven between switching states, the transistor including a control terminal controlled by a control voltage that has a maximum rated limit; and a gate driver coupled to the control terminal by a turn-on current path, the gate driver being configured to control the control voltage in order to drive the transistor between the switching states. The turn-on current path includes a resistor and a Zener diode connected in series, with an anode of the Zener diode connected to the control terminal and a cathode of the Zener diode connected to the resistor. The turn-on current path is configured to provide an on-current to increase the control voltage above a switching threshold. While the transistor is turned on, the Zener diode is configured to limit the control voltage to a voltage level limit that is less than the maximum rated limit.
    Type: Grant
    Filed: September 19, 2022
    Date of Patent: March 5, 2024
    Assignee: Infineon Technologies Austria AG
    Inventors: Kuiwei Xu, Weiwei Cao
  • Patent number: 11923820
    Abstract: An acoustic wave device includes a support substrate, a piezoelectric layer, and an IDT electrode. The piezoelectric layer is directly or indirectly provided on the support substrate. The IDT electrode includes a plurality of electrode fingers and is provided on a main surface of the piezoelectric layer. The thickness of the piezoelectric layer is about 1? or less when a wavelength of an acoustic wave determined by an electrode finger period of the IDT electrode is defined as ?. The support substrate is an A-plane sapphire substrate.
    Type: Grant
    Filed: June 11, 2021
    Date of Patent: March 5, 2024
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Tetsuya Kimura, Shou Nagatomo
  • Patent number: 11916537
    Abstract: Certain aspects of the present disclosure can be implemented in an electroacoustic device. The electroacoustic device generally includes: a substrate; a bottom electrode layer disposed above the substrate; an acoustic mirror stack having a dielectric layer disposed above the bottom electrode layer and a conductive layer disposed above the dielectric layer; a piezoelectric layer disposed above the acoustic mirror stack; and one or more vias disposed between the bottom electrode layer and the conductive layer, the one or more vias electrically coupling the bottom electrode layer and the conductive layer.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: February 27, 2024
    Assignee: RF360 Singapore Pte. Ltd.
    Inventors: Joachim Klett, Thomas Mittermaier
  • Patent number: 11909383
    Abstract: The invention relates to an electrical circuit (1) for transmitting a useful analogue signal, which has a signal transmission path (16) with an input path (2) and an output path (3) and at least one switch (6), with which the useful signal which is carried on the input path (2) can be connected through to the output path (3) or the signal transmission path (16) can be interrupted. According to the invention, a compensation circuit (4) which substantially compensates for a distortion of the useful analogue useful signal generated by the at least one switch (6) when it is switched off (OFF) is provided, wherein the compensation circuit (4) is connected to a control terminal (G) of the at least one switch (6) and comprises at least one non-linear capacitance.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: February 20, 2024
    Inventor: Thomas Meier
  • Patent number: 11909368
    Abstract: A dual mode notch filter for use in a multi-band millimeter wave (mmW) transmitter includes a transmit filter circuit disposed between two amplifiers in a mmW transmit signal path, the transmit filter circuit formed by at least one switch, at least one capacitor, and a double-tuned transformer, the transmit filter circuit having at least two modes configured to selectively filter a spurious signal in at least a first communication band.
    Type: Grant
    Filed: September 7, 2021
    Date of Patent: February 20, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Kai Zhan, Chinmaya Mishra
  • Patent number: 11904805
    Abstract: A tamper-resistant actuator includes a valid input, configured to deliver an input electrical current through a circuit. A high-pass filter is positioned within the circuit that degrades components of the input electrical current that are outside of a predefined current range. Components that are within the predefined current range define an output current. A transistor activates a switch when the output current from the high-pass filter is received by the transistor.
    Type: Grant
    Filed: January 13, 2021
    Date of Patent: February 20, 2024
    Assignee: GHSP, Inc.
    Inventors: Benjamin Cosimo Hunt, John Thomas Bagley
  • Patent number: 11908306
    Abstract: A rescue request apparatus (1) includes a radio communication unit (2) configured to perform radio communication, a trajectory acquisition unit (3) configured to acquire a movement trajectory of the rescue request apparatus when the radio communication cannot be performed by the radio communication unit (2), a user-state determination unit (4) configured to determine whether or not a user of the rescue request apparatus is in a dangerous state, and a drive control unit (5) configured to drive and control the rescue request apparatus so as to trace the movement trajectory acquired by the trajectory acquisition unit (3) when the user-state determination unit (4) determines that the user is in the dangerous state. The radio communication unit (2) transmits a rescue request signal to a pre-registered destination when the radio communication becomes possible.
    Type: Grant
    Filed: November 16, 2018
    Date of Patent: February 20, 2024
    Assignee: NEC Platforms, Ltd.
    Inventor: Naruki Saito
  • Patent number: 11901887
    Abstract: In a semiconductor switch, a resistance value between a current input terminal to which a current is input and a current output terminal from which a current is output decreases as a voltage of a control terminal based on a potential of the current output terminal increases. A booster circuit is disposed on a path extending from the current input terminal to the control terminal. The booster circuit boosts a voltage input from the current input terminal side and applies the boosted voltage to the control terminal. A switch is connected between the control terminal and the current output terminal of the semiconductor switch. The switch is switched off by power consumption. The power consumption stops and the switch switches on if the supply of power to the booster circuit stops.
    Type: Grant
    Filed: August 14, 2020
    Date of Patent: February 13, 2024
    Assignees: AutoNetworks Technologies, Ltd., Sumitomo Wiring Systems, Ltd., Sumitomo Electric Industries, Ltd.
    Inventors: Keisuke Wakazono, Yuuki Sugisawa
  • Patent number: 11899789
    Abstract: A low voltage attack detector includes: a low voltage detector configured to output a low voltage detection flag signal having a high level when a first power supply voltage reaches a first voltage level using a bandgap reference (BGR) circuit including a PMOS transistor and a first bipolar junction transistor (BJT) connected in series between the first power supply voltage and a second power supply voltage; a BGR operation region detector configured to output a malfunction detection flag signal having a high level when the first power supply voltage reaches a second voltage level lower than the first voltage level; and a logic gate configured to output a final low voltage detection flag signal having a high level when at least one of the low voltage detection flag signal and the malfunction detection flag signal has a high level.
    Type: Grant
    Filed: September 9, 2021
    Date of Patent: February 13, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Donghun Heo, Kwangho Kim, Junhyeok Yang
  • Patent number: 11888332
    Abstract: GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Various embodiments of level shift circuits and their inventive aspects are disclosed.
    Type: Grant
    Filed: August 17, 2022
    Date of Patent: January 30, 2024
    Assignee: Navitas Semiconductor Limited
    Inventors: Daniel M. Kinzer, Santosh Sharma, Ju Jason Zhang
  • Patent number: 11881849
    Abstract: A relay circuit may include a solid state relay switch, coupled to an external voltage line and to an charging capacitor; and a solid state relay control circuit, coupled between the charging capacitor and the solid state relay switch. The solid state relay control circuit may be arranged to: turn the solid state relay switch to an OFF state when a capacitor voltage of the charging capacitor falls below a low threshold value; and change the solid state relay switch from the OFF state to an ON state when the capacitor voltage increases above a high threshold value.
    Type: Grant
    Filed: May 3, 2022
    Date of Patent: January 23, 2024
    Assignee: Littelfuse, Inc.
    Inventor: Bret R. Howe