Abstract: A semiconductor integrated circuit of embodiments includes a first MOS transistor configured to control conduction and non-conduction between a reference voltage point and a node, a second MOS transistor connected to the first MOS transistor via the node and configured to apply a voltage equal to or lower than a withstand voltage of the first MOS transistor to the node, a third MOS transistor configured to receive supply of a second voltage higher than the first voltage, and output an output signal of a signal level corresponding to a voltage range of the second voltage, and a switch circuit configured to make a voltage of the node a fixed voltage when the first MOS transistor is in an OFF state.

Abstract: An apparatus that includes a MOS transistor arranged in a well region supplied with a well potential, a temperature sensor configured to generate a control code indicating an ambient temperature, and a voltage generator configured to perform a control operation controlling a level of the well potential responsive to the control code in a first condition and perform a second control operation controlling a level of the well potential regardless of the control code in a second condition.

Abstract: A driving circuit and a driving method are provided. According to embodiments of the present disclosure, a power switch is driven by constant voltage or constant current during different time periods. The power switch is driven by using a first driving current during a Miller platform period, and the power switch is driven by using a second driving current when the Miller platform period ends, where the first driving current is less than the second driving current, so as to optimize EMI, reduce loss and improve efficiency.

Abstract: A method and an integrated circuit for limiting a switchable load current. The integrated circuit includes a main transistor, through which in the conductive state a load current flows for supplying a load and a mirror transistor, a gate terminal of the mirror transistor being electrically connected to a gate terminal of the main transistor and a source terminal of the mirror transistor being electrically connected to a source terminal of the main transistor. The integrated circuit further includes a coupling circuit, which is configured to track a source drain voltage of the mirror transistor as a function of the source drain voltage of the main transistor. A gate control circuit is further provided, which limits the load current through the main transistor on the basis of a drain current through the mirror transistor.

Abstract: An apparatus includes a capacitor coupled to a gate of a power switch, and a negative voltage adjustment device connected to a common node of the capacitor and the gate of the power switch, wherein the negative voltage adjustment device is configured such that after a turn-off signal is applied to the gate of the power switch, a voltage across the capacitor is maintained at a predetermined voltage level through a negative current provided by the negative voltage adjustment device.

Abstract: A coiled electronic component includes: an electronic component body which includes a coil portion having a spiral structure and formed of an electrically conductive material, and electrically conductive connection portions arranged on both ends of the coil portion; and a pair of electrodes for respectively connecting the electrically conductive connection portions to assembly portions arranged on an assembly object. The electrode includes a pair of pinching pieces for pinching the electrically conductive connection portion, and the pair of pinching pieces is opened in a manner that the electrically conductive connection portion is received and fitted therebetween.

Abstract: A drive circuit drives a switch configuring a power converter. The drive circuit divides an inter-terminal voltage of a switch. The drive circuit includes a differential circuit having first and second input terminals to which the divided inter-terminal voltages are inputted. The differential circuit outputs an analog voltage based on a voltage difference between the input terminals. The differential circuit executes reset of the output voltage, and with the voltage difference when reset is canceled after reset is executed as a reference voltage, outputs an analog voltage in which an amount of change from the reference voltage is multiplied by an amplification factor. The drive circuit outputs a binary signal based on comparison results between a threshold and the analog voltage outputted from the differential circuit, and sets a transfer rate of a gate charge of the switch when a driving state is switched, based on the output signal thereof.

Abstract: The invention relates to a circuit arrangement (100), comprising a control circuit (104) and a switch element (101) for switching between a first and a second switching state of the switch element (101). The control circuit (104) is designed to provide a variable pre-control voltage dependent on the switching state of the switch element. The pre-control voltage is a voltage that is switched as the control voltage at the switch element (101) during one of the two switching states. The control circuit (104) is also designed to vary the pre-control voltage during each of the switching states.

Abstract: Disclosed is an RF switch device and, more particularly, an RF switch device that reduces or eliminates a voltage imbalance by implementing at least one stage in a stacked switch device with a different width, and thus the voltage applied to each stage in the OFF state may be more equally distributed among the individual stages.

Abstract: A method for validating operation of a driver integrated circuit includes providing a signal using an output node. The signal is provided using multiple set points in response to a change in state of an input signal. Each set point corresponds to a different phase of a multi-phase transition of the signal. The method includes providing a timer value at an end of a phase of the multi-phase transition and determining whether the signal is in a target signal range of the phase based on the timer value at the end of the phase, a predetermined value defining the target signal range of the phase, and a predetermined time limit for the phase. A current through the output node may be provided using the multiple set points, and a voltage on the output node may have the multi-phase transition.

Abstract: The present disclosure provides designs and techniques to improve turn “off” times of a bootstrapped switch, maximizing the total “on” time of the bootstrapped switch. The techniques described herein provide a protection device coupled to the bootstrapped switch. The protection device may be controlled by an input voltage to the bootstrapped switch during a boosting phase and may be controlled by a constant voltage during a non-boosting phase. The techniques for reducing turn “off” times are particularly useful in high-speed applications, such as high-speed, low-voltage analog-to-digital converters.

Abstract: A circuit to multiplex supply voltages may include a set of chains of transistors. Each chain of transistors may correspond to a voltage supply that is desired to be multiplexed and may include a set of transistors coupled in series. A first end terminal of each chain of transistors may be coupled to a corresponding voltage supply, and a second end terminal of each chain of transistors may be coupled to an output terminal of the circuit. A given supply voltage may be selected by turning on transistors in a chain of transistors that corresponds to the given supply voltage and turning off transistors in other chains of transistors.

Abstract: A relay circuit may include a solid state relay switch, coupled to an external voltage line and to an charging capacitor; and a solid state relay control circuit, coupled between the charging capacitor and the solid state relay switch. The solid state relay control circuit may be arranged to: turn the solid state relay switch to an OFF state when a capacitor voltage of the charging capacitor falls below a low threshold value; and change the solid state relay switch from the OFF state to an ON state when the capacitor voltage increases above a high threshold value.

Abstract: A circuit device includes a control circuit configured to control a transistor current based on a detected temperature. The detected temperature is a temperature detected by a temperature sensor circuit that detects a temperature of a transistor. The transistor charges a load to which a power supply voltage is supplied. The transistor current is a current flowing through the transistor during charging. The control circuit reduces the transistor current when the detected temperature is higher than a first threshold value, and increases the transistor current when the detected temperature is lower than a second threshold value lower than the first threshold value.

Abstract: A circuit comprises first and second input supply nodes configured to receive a supply voltage therebetween. The circuit comprises a high-side driver circuit configured to be coupled to a high-side switch and produce a first signal between first and second high-side output nodes. The circuit comprises a low-side driver circuit configured to be coupled to a low-side switch and produce a second signal between first and second low-side output nodes. The circuit comprises a floating node configured to receive a floating voltage applied between the floating node and the second high-side output node, a bootstrap diode between the first input supply node and an intermediate node, and a current limiter circuit between the intermediate node and the floating node and configured to sense the floating voltage and counter a current flow from the intermediate node to the floating node as a result of the floating voltage reaching a threshold value.

Abstract: Various examples are provided related to supercascode power switches that can be used in, e.g., HV and MV applications. This disclosure introduces a cascaded supercascode (CSC) power switch which can include a series of unit supercascode (USC) circuits; a control switch coupled in series with the series of USC circuits; and an external balancing network coupled to each of the n USC circuits. The series has a plurality of USC circuits, with each of the USC circuits including first and second switches coupled in series and an internal balancing network coupled across the first and second switches. A source of each of the USC circuits is a source of the first switch. The internal balancing network can include a capacitor connected between a gate of the second switch and the source of the first switch and a diode connected in parallel with the capacitor.

Abstract: A comparator circuit configured to output an output voltage at a first logic level, upon an input voltage exceeding a first threshold voltage, and output the output voltage at a second logic level, upon the input voltage dropping below a second threshold voltage lower than the first threshold voltage. The comparator circuit includes a converter circuit configured to convert the input voltage of the comparator circuit into a first voltage and a second voltage lower than the first voltage, and a logic circuit configured to output a voltage, as the output voltage of the comparator circuit, that is at the first logic level, upon the first voltage exceeding a third threshold voltage, and at the second logic level, upon the second voltage dropping below a fourth threshold voltage lower than the third threshold voltage.

Abstract: A method includes: forming first, second, and third NWs; forming form first to fourth transistors in corresponding first to fourth groups of active regions, connecting selected transistors amongst the first and second transistors to form first and second input circuits respectively receiving a first input signal in a first domain and a second input signal in the first domain; connecting selected transistors amongst the first and third transistors and amongst the first and fourth transistors to respectively form a first single bit level shifter (SBLS) and a second SBLS; each SBLS operates in the second domain and receives correspondingly versions of the first and second input signals; and connecting selected transistors amongst the first and third transistors to form a control circuit for toggling the first and second SBLSs between a normal and a standby state, a portion of the control circuit and the first SBLS sharing the second NW.

Abstract: RF transistors manufactured using a bulk CMOS process exhibit non-linear drain-body and source-body capacitances which degrade the linearity performance of the RF circuits implementing such transistors. The disclosed methods and devices address this issue and provide solutions based on implementing two or more bias voltages in accordance with the states of the transistors. Various exemplary RF circuits benefiting from the described methods and devices are also presented.

Abstract: An apparatus includes a comparator. The comparator includes first and second pregain stages, and a switch network coupled to the first and second pregain stages. A plurality of switches in the switch network are operable to provide a feedback path around at least one of the first and second pregain stages. The comparator further includes a latch coupled to the second pregain stage.