Abstract: An elastic wave device includes a high-acoustic-velocity member, a low-acoustic-velocity film, a piezoelectric film, and am interdigital transducer electrode stacked in this order. The interdigital transducer electrode includes an intersecting region and outer edge regions. The intersecting region includes a central region located in the middle of the intersecting region in the direction in which electrode fingers extend and the inner edge regions located at the respective outer side portions of the central region. The electrode fingers in the inner edge regions have a larger thickness than in the central region. Each electrode finger has an incrased thickness portion. The increased thickness portion is made of a metal having a density d of about 5.5 g/cm3 or more and has a film thickenss equal to or smaller than a wavelength-normalized film thickness represented by T (%)=?0.1458d+4.8654.

Abstract: A high frequency switch configured to switch paths of differential signals arranged in an integrated circuit. The high frequency switch includes a pair of pole terminals and a plurality of pairs of throw terminals. The pair of pole terminals constitutes one port. Each pair of throw terminals constitutes another port.

Abstract: A multi-bit level-shifter (MBLS) includes two or more input circuits correspondingly configured to operate in a first voltage domain. The MBLS also includes two or more single bit level shifters (SBLSs) electrically coupled correspondingly to the two or more input circuits, and correspondingly configured to operate in a second voltage domain. The MBLS also includes a control circuit configured to toggle each of the two or more SBLSs between a normal mode and a standby mode according to a toggle-control signal received from the control circuit.

Abstract: The application provides a gate driver circuit and a multiphase intelligent power module. When a first switch unit is closed, a power supply charges a first capacitor and a second capacitor, and a first buffer provides a gate voltage for a first power transistor. The first capacitor can improve the potential of the gate of the first power transistor, so that the first power transistor is turned on; second capacitor can provide a negative turn-off voltage for the first power transistor, and can adaptively convert external voltage into voltage that can drive the power transistor. Moreover, the circuit can be realized easily and the voltage of the first power transistor is stable.

Abstract: A gate-driving circuit for turning on and off a switch device including a gate terminal coupled to a driving node, a drain terminal coupled to a power node, and a source terminal is provided. The gate-driving circuit includes a driving switch and a voltage control circuit. The driving switch includes a gate terminal coupled to a control node, a drain terminal coupled to the power node, and a source terminal coupled to the driving node. The voltage control circuit is coupled between the control node and the driving node. When a positive pulse is generated at the control node, the voltage control circuit provides the positive pulse to the driving node with a time delay.

Abstract: A drive circuit for a power semiconductor circuit may include input contact means for inputting a control signal, the control signal representing a switching command for the power semiconductor circuit, and also at least one output contact means, to which the power semiconductor circuit is connectable and which serves for outputting a switching signal to the power semiconductor circuit. Furthermore, the drive circuit comprises current path connection means for connecting the drive circuit to a current path to be switched by the power semiconductor circuit, and means for galvanically isolating the input contact means from the output contact means and the current path connection means. Circuit means which output a switching signal that switches on the power semiconductor circuit if a control signal representing the switch-on command for the power semiconductor circuit is input at the input contact means and also voltage is present at the current path connection means.

Abstract: A design technique is disclosed that divides up a cellular power switch into different size segments. Each segment is driven by a different driver circuit. The selection of the combination of segments is made to minimize the combined conduction and switching losses of the power switch. For example, for very light loads, switching losses dominate so only a small segment is activated for driving the load. For medium and high load currents, conduction losses become more significant, so additional segments are activated to minimize the total losses. In one embodiment, the number of cells in the segments is binary weighted, such as 1×, 2×, and 4×, so that there are seven different combinations of segments. The drivers may be configured to achieve the same or different slew rates of the segments, such as to reduce transients. The segments may all be in the same die or a plurality of dies.

Abstract: A resonant switch with a first port and a second port has a capacitor connected thereto. A triple inductor network has a center inductor connected to the first port and the second port, and first and second peripheral inductors each electromagnetically coupled thereto. In a deactivated state, the center inductor and the capacitor define a parallel resonance at a predefined operating frequency range, and in an activated state, insertion loss associated with the center inductor is substantially minimized to metallic trace loss attributable thereto.

Abstract: Embodiments of the present invention provide a switching circuit. The circuit comprises: a charging sub-circuit, which has a first input end and an output end; a switching sub-circuit, which has a first end, a second end, and a control end, wherein the control end of the switching sub-circuit is connected to the output end of the charging sub-circuit; and a function sub-circuit, which is connected to the first end or the second end of the switching sub-circuit, and has a first node, wherein an operating voltage of the first node is higher than an input voltage of an input power supply, the switching sub-circuit comprises one or more NMOS switches, and the first input end of the charging sub-circuit is connected to the first node.

Abstract: A switching circuit comprising a transistor (23) and a drive component both for controlling the transistor and also for limiting the power supply current (Ia) suppled to a load (22), the drive component being arranged both to receive a control voltage (VH) and also: when the control voltage (VH) is disconnection signal, to generate a drive voltage (Vp) that causes the transistor to occupy a non-conductive state; when the control voltage (VH) is a connection signal and the power supply current (Ia) cannot reach a predefined current threshold, to generate drive voltage (Vp) that causes the transistor to occupy saturated conditions; and when the control voltage (VH) is a connection signal and the power supply current (Ia) can reach a predefined current threshold, to generate a drive voltage (Vp) that causes the transistor to occupy linear conditions, such that the power supply current is regulated so that it does not exceed the predefined current threshold.

Abstract: A device for driving a control terminal of a transistor includes an input terminal, a transformer including an input winding and an output winding, the input winding being coupled to the input terminal, an n-stage buffer circuit configured to generate a drive signal for the control terminal of the transistor, the n-stage buffer circuit being coupled to a first end of the output winding, and a positive feedback path coupled to an output of a stage of the n-stage buffer circuit to provide a DC offset to an input of the n-stage buffer circuit.

Abstract: Circuits, systems, devices, and methods related to a switch with an integrated Schottky barrier contact are discussed herein. For example, a radio-frequency switch can include an input node, an output node, and a transistor connected between the input node and the output node. The transistor can be configured to control passage of a radio-frequency signal from the input node to the output node. The transistor can include a first Schottky diode integrated into a drain of the transistor and/or a second Schottky diode integrated into a source of the transistor. The first Schottky diode and/or the second Schottky diode can be configured to compensate a non-linearity effect of the radio-frequency switch.

Abstract: A voltage power switch includes circuitry configured to output a known voltage. The voltage power switch includes a lock circuit configured to output a known state and a voltage level shifter configured to receive an input, the input being based on the known state output by the lock circuit. The voltage power switch, using an output circuit, is configured to output a known voltage level based on an output of the voltage level shifter, wherein the known voltage is one of a high voltage VHI for a fuse programing period or a first non-zero intermediate voltage VMID1 for a non-fuse programming period.

Abstract: A positive-logic FET switch stack that does not require a negative bias voltage, exhibits high isolation and low insertion/mismatch loss, and may withstand high RF voltages. Embodiments include a FET stack comprising series-coupled positive-logic FETs (i.e., FETs not requiring a negative voltage supply to turn OFF), series-coupled on at least one end by an “end-cap” FET of a type that turns OFF when its VGS is zero volts. The one or more end-cap FETs provide a selectable capacitive DC blocking function or a resistive signal path. Embodiments include a stack of FETs of only the zero VGS type, or a mix of positive-logic and zero VGS type FETs with end-cap FETs of the zero VGS type. Some embodiments withstand high RF voltages by including combinations of series or parallel coupled resistor ladders for the FET gate resistors, drain-source resistors, body charge control resistors, and one or more AC coupling modules.

Abstract: A signal is caused to have a small amplitude without increasing a voltage source, and power consumption is reduced. A semiconductor circuit includes a driver, and a pulse control circuit that controls the driver. The driver has a configuration in which first and second transistors are connected. The pulse control circuit supplies a first control signal to the first transistor, and supplies a second control signal to the second transistor. The first and second control signals to be supplied from the pulse control circuit are different in a pulse width from each other. Therefore, the pulse control circuit reduces an output amplitude of the driver.

Abstract: A clock distribution circuit configured to output a clock signal includes a first circuit configured to use a reference clock signal to provide first and second reference signals, wherein the second reference signal indicates whether the first reference signal is locked with the reference clock signal; a second circuit configured to use the reference clock signal to provide an output signal and an indication signal indicative whether the output signal is locked with the reference clock signal; and a monitor circuit, coupled to the first and second circuits, and configured to use at least one of the first reference signal, the second reference signal, the output signal, and the indication signal to determine whether the second circuit is functioning correctly.

Abstract: A common gate resistor bypass arrangement for a stacked arrangement of FET switches, the arrangement including a series combination of an nMOS transistor and a pMOS transistor connected across a common gate resistor. During at least a transition portion of the transition state of the stacked arrangement of FET switches, the nMOS transistor and the pMOS transistor are both in an ON state and bypass the common gate resistor. On the other hand, during at least a steady state portion of the ON steady state and the OFF steady state of the stacked arrangement of FET switches, one of the nMOS transistor and the pMOS transistor is in an OFF state and the other of the nMOS transistor and the pMOS transistor is in an ON state, thus not bypassing the common gate resistor.

Abstract: A switching circuit includes: a normally-off junction field-effect GaN transistor including source, drain, and gate terminals; a drive device of one output type electrically connected to the gate terminal; a first rectifier, between the source terminal and the gate terminal, including an anode on a source terminal side and a cathode on a gate terminal side; a capacitor between a cathode side of the first rectifier and the drive device; a first resistor between the capacitor and the drive device; a second resistor, one side of the second resistor being connected to the drive device, another side of the second resistor being connected between the cathode side of the first rectifier and the capacitor; and a second rectifier including an anode on a capacitor side and a cathode on a drive device side. No resistor is provided between the cathode side of the second rectifier and the drive device.

Abstract: An electric vehicle control device includes a plurality of drive control systems that controls travelling of an electric vehicle. Each of the drive control systems includes an induction motor, an inverter that drives the induction motor, and a controller that controls the inverter. Each of the controllers of the plurality of drive control systems includes a miswiring detector that calculates a torque estimation value on a basis of motor currents and voltage command values and detects miswiring between the induction motor and the inverter on a basis of the calculated torque estimation value and the torque command value.

Abstract: A capless impedance tuner can include first node and second nodes, a first series path, a second series path, and an inductance path, each between the first node and the second node and including a switch to allow the path to couple or uncouple the first and second nodes. Each series path can be configured to allow a substantially continuous flow of a direct current between the first node and the second node when coupled. The tuner can further include a shunt path with a switch to allow coupling or uncoupling of the second node and ground. The tuner can further include a switchable grounding path implemented along the inductance path and configured to allow the inductance path to function as a series inductance path between the first and second nodes, or as a shunt inductance path between the ground and a node along the inductance path.