Abstract: A memory array comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Intervening material is laterally-between and longitudinally-along immediately-laterally-adjacent of the memory blocks. The intervening material in a lowest of the conductive tiers comprises intervenor material. Bridges extend laterally-between the immediately-laterally-adjacent memory blocks. The bridges comprise bridging material that is of different composition from that of the intervenor material. The bridges are longitudinally-spaced-along the immediately-laterally-adjacent memory blocks by the intervenor material and extend laterally into the immediately-laterally-adjacent memory blocks. Other embodiments, including method, are disclosed.

Abstract: The disclosure provides a display panel and a display device. The display panel includes a first substrate and a second substrate, the second substrate has an organic electroluminescent device, an anode layer of the organic electroluminescent device is away from the first substrate and a cathode layer thereof is closer to the first substrate than the anode layer; the cathode layer is electrically connected to an auxiliary electrode on a light entering surface of the first substrate through multiple conductive spacers, the cathode layer is a transparent electrode layer; the auxiliary electrode has a resistance smaller than that of the cathode layer of the organic electroluminescent device; the auxiliary electrode is a grid-shaped auxiliary electrode and in a non-display region, the auxiliary electrode is opaque; the multiple conductive spacers includes first conductive spacers on the auxiliary electrode and second conductive spacers on the cathode layer of the second substrate.

Abstract: Image sensors are provided. An image sensor includes a substrate including a plurality of pixel areas. The substrate has a first surface and a second surface that is opposite the first surface. The image sensor includes a deep pixel isolation region extending from the second surface of the substrate toward the first surface of the substrate and separating the plurality of pixel areas from each other. The image sensor includes an amorphous region adjacent a sidewall of the deep pixel isolation region. Moreover, the image sensor includes an electron suppression region between the amorphous region and the sidewall of the deep pixel isolation region.

Abstract: A semiconductor device with resistive memory includes a bottom electrode disposed on a base structure, the bottom electrode having a structure that tapers up from the base structure to a tip of the bottom electrode. The semiconductor device also includes sidewall spacers on the sides of the bottom electrode, an interlayer dielectric deposition (ILD) outside the sidewall spacers, and a top dielectric layer disposed over the bottom electrode, and the sidewall spacers. The semiconductor device further includes a top electrode deposited over the bottom electrode within the sidewall spacers. A filament formation region is formed at the tip of the bottom electrode.

Abstract: A semiconductor device includes a metal substrate including a through-hole aperture having a multi-size cavity including a larger area first cavity portion above a smaller area second cavity portion that defines a first ring around the second cavity portion, where the first cavity portion is sized with area dimensions to receive a semiconductor die having a top side with circuitry coupled to bond pads thereon and a back side with a metal (BSM) layer thereon. The semiconductor die is mounted top side up with the BSM layer on the first ring. A metal die attach layer directly contacts the BSM layer, sidewalls of the bottom cavity portion, and a bottom side of the metal substrate.

Abstract: A chip includes a semiconductor body coupled to a first and a second load terminal. The semiconductor body includes an active region including a plurality of breakthrough cells, each of the breakthrough cells includes: an insulation structure; a drift region; an anode region, the anode region being electrically connected to the first load terminal and disposed in contact with the first load terminal; a first barrier region arranged in contact with each of the anode region and the insulation structure, where the first barrier region of the plurality of breakthrough cells forms a contiguous semiconductor layer; a second barrier region separating each of the anode region and at least a part of the first barrier region from the drift region; and a doped contact region arranged in contact with the second load terminal, where the drift region is positioned between the second barrier region and the doped contact region.

Abstract: Semiconductor packages including a computing device with a heat source, and related devices and methods, are disclosed herein. For example, the computing device may have a heatsink physically and thermally coupled with the heat source. The heatsink may include a structural element internal to the heatsink. The structural element may cause a surface of the heatsink to deform to a non-planar configuration when the heatsink is coupled to the heat source.

Abstract: A static random access memory (SRAM) cell includes a first gate and a second gate each extending in a first direction. A first gap separates the first gate from the second gate in the first direction. The SRAM cell includes a Vcc contact extending in the first direction. A second gap separates the Vcc contact and the first gate in a second direction perpendicular to the first direction. No segment of the Vcc contact overlaps with the first gap in the first direction. The SRAM cell includes a Vss contact extending in the first direction. A third gap separates the Vss contact from the first gate in the second direction. A segment of the Vss contact is disposed to the first gap. The Vss contact is smaller than the Vcc contact in the second direction.

Abstract: The disclosure provides an electronic imaging device and a manufacturing method thereof, a flexible electronic compound eye and a manufacturing method thereof. The electronic imaging device includes a base substrate and a plurality of photosensitive units arranged in an array on a surface of the base substrate, at least one of the photosensitive units includes a photodiode and a rectifier diode connected in series. The photodiode includes a first conduction type doped region and a second conduction type doped region, the rectifier diode includes a first conduction type doped region and a second conduction type doped region, and the first conduction type doped region of the photodiode and the first conduction type doped region of the rectifier diode are electrically connected to each other.

Abstract: One illustrative device disclosed herein includes a memory cell positioned in a first opening in at least one layer of insulating material. The memory cell comprises a bottom electrode, a memory state material positioned above the bottom electrode and an internal sidewall spacer positioned within the first opening, wherein the internal sidewall spacer defines a spacer opening. The device also comprises a top electrode positioned within the spacer opening.

Abstract: A method for forming a deep trench isolation structure for a CMOS image sensor includes providing a trench that extends from a first side toward a second side of a semiconductor substrate. The trench has an opening on the first side and a bottom and sides. A conformal layer of B-doped oxide is deposited on the bottom and sides of the trench and is less than half a width of the trench leaving a depthwise recess in the trench. A second material is deposited on the conformal layer of B-doped oxide in the trench filling the recess in the trench to the first side. The conformal layer of B-doped oxide is annealed driving boron from the conformal layer of B-doped oxide to the semiconductor substrate forming a B-doped region as a passivation layer juxtaposed next to the conformal layer of B-doped oxide having negative fixed charges.

Abstract: The present technology relates to a substrate, a manufacturing method, and an electronic apparatus which enable prevention of damage to a semiconductor component. The substrate includes a second region that is disposed inside a first region in which a semiconductor component is arranged and that is surrounded by a connection part and a slit, the connection part having a spot facing on a side of a surface on which the semiconductor component is arranged. The present technology is applicable to manufacturing of electronic apparatuses such as a package substrate on which a semiconductor component that is an image sensor or the like is mounted, a digital camera equipped with a semiconductor component for capturing images by receiving the light, and a mobile phone having an image capturing function.

Abstract: A technique relates to a semiconductor device. A source or drain (S/D) contact liner is formed on one or more S/D regions. Annealing is performed to form a silicide layer around the one or more S/D regions, the silicide layer being formed at an interface between the S/D contact liner and the S/D regions. A block layer is formed into a pattern over the one or more S/D regions, such that a portion of the S/D contact liner is protected by the block layer. Unprotected portions of the S/D contact liner are removed, such that the S/D contact liner protected by the block layer remains over the one or more S/D regions. The block layer and S/D contacts are formed on the S/D contact liner over the one or more S/D regions.

Abstract: A semiconductor device including field-effect transistors (finFETs) and fin capacitors are formed on a silicon substrate. The fin capacitors include silicon fins, one or more electrical conductors between the silicon fins, and insulating material between the silicon fins and the one or more electrical conductors. The fin capacitors may also include insulating material between the one or more electrical conductors and underlying semiconductor material.

Abstract: An imaging element includes a photoelectric conversion section that includes a first electrode, a photoelectric conversion layer, and a second electrode stacked on one another. An inorganic oxide semiconductor material layer is formed between the first electrode and the photoelectric conversion layer. The inorganic oxide semiconductor material layer includes indium (In) atoms, gallium (Ga) atoms, tin (Sn) atoms, and zinc (Zn) atoms.

Abstract: An electronic power conversion component includes an electrically conductive package base comprising a source terminal, a drain terminal, at least one I/O terminal and a die-attach pad wherein the source terminal is electrically isolated from the die-attach pad. A GaN-based semiconductor die is secured to the die attach pad and includes a power transistor having a source and a drain, wherein the source is electrically coupled to the source terminal and the drain is electrically coupled to the drain terminal. A plurality of wirebonds electrically couple the source to the source terminal and the drain to the drain terminal. An encapsulant is formed over the GaN-based semiconductor die, the plurality of wirebonds and at least a top surface of the package base.

Abstract: A display device includes a first substrate including a display area and a non-display area, a display element disposed on the first substrate in the display area, a first sealing portion disposed on the first substrate in the non-display area, a second substrate facing the first substrate in a thickness direction, a hole defined through the first substrate and the second substrate along the thickness direction in the display area, and a second sealing portion disposed between the first substrate and the second substrate and enclosing the hole.

Abstract: In some embodiments, the present disclosure relates to a display device that includes a reflector electrode coupled to an interconnect structure. An isolation structure is disposed over the reflector electrode, and a transparent electrode is disposed over the isolation structure. Further, an optical emitter structure is disposed over the transparent electrode. A via structure extends from a top surface of the isolation structure to the reflector electrode and comprises an outer portion that directly overlies the top surface of the isolation structure. A hard mask layer is arranged directly between the top surface of the isolation structure and the outer portion of the via structure.

Abstract: A photodetection film includes at least one lower photodiode and upper photodiode layered members. The at least one lower photodiode layered member includes lower first-type, intrinsic and second-type semiconductor layers. The at least one upper photodiode layered member is disposed on the at least one lower photodiode layered member and includes upper first-type, intrinsic and second-type semiconductor layers. The upper intrinsic semiconductor layer has an amorphous silicon structure. The lower intrinsic semiconductor layer has a structure selected from one of a microcrystalline silicon structure, a microcrystalline silicon-germanium structure, and a non-crystalline silicon-germanium structure.

Abstract: An optoelectronic component and an assembly with an optoectronic component are disclosed. In an embodiment an optoelectronic component includes an optical element with an outer surface and an inner surface that faces away from the outer surface, wherein the inner surface includes a first region of the optical element, in which the inner surface is flat, wherein the inner surface includes a second region of the optical element, wherein the second region adjoins the first region, and wherein the inner surface includes a third region of the optical element, in which the inner surface extends from the second region in the direction of a housing.