Abstract: A semiconductor light emitting device includes a conductive substrate and a first metal layer disposed on the substrate. The first metal layer is formed so as to be electrically connected with the substrate, and the first metal layer includes an Au based material. A joining layer is formed on the first metal layer. The joining layer includes a second metal layer including Au and a third metal layer including Au. A metallic contact layer and an insulating layer are formed on the joining layer. A semiconductor layer is formed on the metallic contact layer and the insulating layer and includes a red-based light emitting layer. An electrode is formed on the semiconductor layer and is made of metal. The insulating layer includes a patterned aperture, and at least a part of the metallic contact layer is formed in the aperture.

Abstract: There is provided a solid-state imaging device including: an imaging pixel including a photoelectric conversion unit which receives incident light; and a phase difference detection pixel including the photoelectric conversion unit and a light shielding unit which shields some of the light incident to the photoelectric conversion unit, in which the imaging pixel further includes a high refractive index film which is formed on the upper side of the photoelectric conversion unit, and the phase difference detection pixel further includes a low refractive index film which is formed on the upper side of the photoelectric conversion unit.

Abstract: Photosensors may be formed on a front side of a semiconductor substrate. An optical refraction layer having a first refractive index may be formed on a backside of the semiconductor substrate. A grid structure including openings is formed over the optical refraction layer. A masking material layer is formed over the grid structure and the optical refraction layer. The masking material layer may be anisotropically etched using an anisotropic etch process that collaterally etches a material of the optical refraction layer and forms non-planar distal surface portions including random protrusions on physically exposed portions of the optical refraction layer. An optically transparent layer having a second refractive index that is different from the first refractive index may be formed on the non-planar distal surface portions of the optical refraction layer. A refractive interface refracts incident light in random directions, and improves quantum efficiency of the photosensors.

Abstract: A quantum dot structure, a radiation conversion element and a light emitting device are disclosed. In an embodiment a quantum dot structure includes an active region configured to emit radiation, a barrier region surrounding the active region and a trap region spaced apart from the active region, wherein a band edge of the trap region forms a trap configuration with respect to the barrier region for at least one type of charge carrier.

Abstract: A static random access memory (SRAM) cell includes a first gate and a second gate each extending in a first direction. A first gap separates the first gate from the second gate in the first direction. The SRAM cell includes a Vcc contact extending in the first direction. A second gap separates the Vcc contact and the first gate in a second direction perpendicular to the first direction. No segment of the Vcc contact overlaps with the first gap in the first direction. The SRAM cell includes a Vss contact extending in the first direction. A third gap separates the Vss contact from the first gate in the second direction. A segment of the Vss contact is disposed to the first gap. The Vss contact is smaller than the Vcc contact in the second direction.

Abstract: The disclosure provides LED display panel and manufacturing method thereof. LED display panel includes: substrate; LED on substrate; pixel defining layer defining pixel opening on substrate, the LED being within pixel opening; and first encapsulation layer on light emitting side of LED. Portion of first encapsulation layer within pixel opening includes sidewall inclined with respect to substrate, surface of sidewall close to LED includes first portions and second portions alternately arranged in direction away from LED and connected to each other, and inclination angles of first portions with respect to substrate are smaller than those of second portions with respect to substrate. Refractive index of material of first encapsulation layer is greater than refractive index of material of each of layer structures directly on both sides of first encapsulation layer in direction perpendicular to substrate.

Abstract: A method for producing a 3D memory device including: providing a first level including a single crystal layer and control circuits, where the control circuits include a plurality of first transistors; forming at least one second level above the first level; performing a first etch step including etching holes within the second level; performing processing steps to form a plurality of first memory cells within the second level, where each of the first memory cells include one of a plurality of second transistors, where the control circuits include memory peripheral circuits, where at least one first memory cell is at least partially atop a portion of the memory peripheral circuits, and where fabrication processing of the first transistors accounts for a temperature and time associated with processing the second level and the plurality of second transistors by adjusting a process thermal budget of the first level accordingly.

Abstract: It is an object of the present invention to improve light source efficiency of “a light-emitting device capable of realizing a natural, vivid, highly visible and comfortable appearance of colors or an appearance of objects” already arrived at by adopting a spectral power distribution having a shape completely different from the shape of conventionally known spectral power distributions while maintaining favorable color appearance characteristics.

Abstract: A flexible display device is manufactured with high yield. A display device having high resistance to repeated bending is provided. The display device is manufactured by forming a separation layer over a support substrate; forming, over the separation layer, an inorganic insulating layer including a first portion and a second portion; forming a display element over the inorganic insulating layer to be overlapped with the first portion; forming a connection electrode over the inorganic insulating layer to be overlapped with the second portion; sealing the display element; separating the support substrate and the inorganic insulating layer using the separation layer; attaching a substrate to the inorganic insulating layer to be overlapped with the first portion; and etching the second portion using the substrate as a mask to expose the connection electrode.

Abstract: Embodiments of a three-dimensional capacitor for a memory device and fabrication methods are disclosed. The method includes forming, on a first side of a first substrate, a peripheral circuitry having a plurality of peripheral devices, a first interconnect layer, a deep well and a first capacitor electrode. The method also includes forming, on a second substrate, a memory array having a plurality of memory cells and a second interconnect layer, and bonding the first interconnect layer of the peripheral circuitry with the second interconnect layer of the memory array. The method further includes forming, on a second side of the first substrate, one or more trenches inside the deep well, disposing a capacitor dielectric layer on sidewalls of the one or more trenches, and forming capacitor contacts on sidewalls of the capacitor dielectric layer inside the one or more trenches.

Abstract: A semiconductor device including a transistor section and a diode section, the semiconductor device having: a temperature sensing section; a neighboring transistor section adjacent to the temperature sensing section; a neighboring diode section adjacent to the temperature sensing section; and a first non-neighboring diode section that is not adjacent to the temperature sensing section, wherein the first non-neighboring diode section has a pattern different from the pattern of the neighboring diode section in the top view is provided.

Abstract: A semiconductor structure capable of real-time spatial sensing of nanoparticles within a nanofluid is provided. The structure includes an array of gate structures. An interlevel dielectric material surrounds the array of gate structures. A vertical inlet channel is located within a portion of the interlevel dielectric material and on one side of the array of gate structures. A vertical outlet channel is located within another portion of the interlevel dielectric material and on another side of the array of gate structures. A horizontal channel that functions as a back gate is in fluid communication with the vertical inlet and outlet channels, and is located beneath the array of gate structures. A back gate dielectric material portion lines exposed surfaces within the vertical inlet channel, the vertical outlet channel and the horizontal channel.

Abstract: There is provided imaging devices and methods of forming the same, including a stacked structure body including a first electrode, a light-receiving layer formed on the first electrode, and a second electrode formed on the light-receiving layer, where the second electrode comprises an amorphous oxide comprising at least one of zinc and tungsten, and where the second electrode is transparent and electrically conductive and has absorption characteristics of 20% or more at a wavelength of 300 nm.

Abstract: A chip production method includes a first step of setting a first cutting line and a second cutting line on a substrate including a plurality of functional elements, a second step of forming a mask on the substrate such that the functional elements are covered and an intersection region including an intersection of the first cutting line and the second cutting line is exposed, a third step of removing the intersection region from the substrate and forming a penetration hole by etching the substrate using the mask, a fourth step of forming a modified region in the substrate along the first cutting line, a fifth step of forming a modified region in the substrate along the second cutting line, and a sixth step of forming chips by cutting the substrate along the first cutting line and the second cutting line.

Abstract: A thin film transistor and a manufacturing method thereof, an array substrate and a manufacturing method thereof, and a display panel are provided. The thin film transistor includes an active layer and a wire grid which is disposed at least on a surface of an active region of the active layer and is made of a conductive material. The active layer includes a source region, a drain region, and the channel region between the source region and the drain region. The wire grid includes a plurality of wire grid sections which are spaced apart from each other, and in a direction from the source region to the drain region, a length of the channel region is longer than a length of the wire grid section.

Abstract: An array of vertically stacked tiers of memory cells includes a plurality of horizontally oriented access lines within individual tiers of memory cells and a plurality of horizontally oriented global sense lines elevationally outward of the tiers. A plurality of select transistors is elevationally inward of the tiers. A plurality of pairs of local first and second vertical lines extends through the tiers. The local first vertical line within individual of the pairs is in conductive connection with one of the global sense lines and in conductive connection with one of the two source/drain regions of one of the select transistors. The local second vertical line within individual of the pairs is in conductive connection with another of the two source/drain regions of the one select transistor. Individual of the memory cells include a crossing one of the local second vertical lines and one of the horizontal access lines and programmable material there-between.

Abstract: A method for fabricating an electronic device includes fixing a rear face of an integrated-circuit chip to a front face of a support wafer. An infused adhesive is applied in the form of drops or segments that are separated from each other. A protective wafer is applied to the infused adhesive, and the infused adhesive is cured. The infused adhesive includes a curable adhesive and solid spacer elements infused in the curable adhesive. A closed intermediate peripheral ring is deposited on the integrated-circuit chip outside the cured infused adhesive, and an encapsulation block is formed such that it surrounds the chip, the protective wafer and the closed intermediate peripheral ring.

Abstract: A package for mounting a light emitting element includes: a first lead electrode having, in a plan view, a first region, a second region surrounding a periphery of the first region having a width of 110 ?m or more and a thickness greater than that of the first region, and a third region partially surrounding a periphery of the second region and having a thickness smaller than that of the second region; a second lead electrode spaced apart from the first lead electrode; and a resin molded body fixing a portion of each of the first and second lead electrodes. A portion of each of the first and second lead electrodes and a portion of the resin molded body exposed therebetween form a bottom surface of a recess.

Abstract: A device and method of utilizing a repeater circuit to extend the viable length of an interconnect bridge. Integrated circuit packages using a repeater circuit in a repeater die, embedded in a substrate, and included in an interconnect bridge are show. Methods of connecting semiconductor dies using interconnect bridges coupled with repeater circuits are shown.

Abstract: A FinFET and methods for forming a FinFET are disclosed. A method includes forming a semiconductor fin on a substrate, implanting the semiconductor fin with dopants, and forming a capping layer on a top surface and sidewalls of the semiconductor fin. The method further includes forming a dielectric on the capping layer, and forming a gate electrode on the dielectric.