Abstract: The present application provides a thin film transistor and a method of fabricating the same, an array substrate and a display device. The thin film transistor includes: a gate electrode; an active layer including a first portion made of polysilicon and a second portion made of amorphous silicon; a source electrode and a drain electrode; and an ohmic contact layer. The second portion of the active layer is in contact with the source electrode and the drain electrode through the ohmic contact layer.

Abstract: A multi-layer substrate with metal layers as a moisture diffusion barrier for reduced electrical performance degradation over time after moisture exposure and methods of design and manufacture. The method includes determining a diffusion rate of an insulator material provided between an upper metal layer and an underlying signal line. The method further includes calculating a diffusion distance between a plane opening of the upper metal layer and the underlying signal line using the diffusion rate of the insulator material.

Abstract: A manufacturing method of a flip-chip nitride semiconductor light emitting element includes a step of providing a nitride semiconductor light emitting element structure; a protective layer forming step; a first resist pattern forming step; a protective layer etching step; a first metal layer forming step; a first resist pattern removing step; a third metal layer forming step; a second resist pattern forming step; a second metal layer forming step; a second resist pattern removing step; and a third metal layer removing step.

Abstract: A multi-layer substrate with metal layers as a moisture diffusion barrier for reduced electrical performance degradation over time after moisture exposure and methods of design and manufacture. The method includes determining a diffusion rate of an insulator material provided between an upper metal layer and an underlying signal line. The method further includes calculating a diffusion distance between a plane opening of the upper metal layer and the underlying signal line using the diffusion rate of the insulator material.

Abstract: A FinFET and methods for forming a FinFET are disclosed. A method includes forming a semiconductor fin on a substrate, implanting the semiconductor fin with dopants, and forming a capping layer on a top surface and sidewalls of the semiconductor fin. The method further includes forming a dielectric on the capping layer, and forming a gate electrode on the dielectric.

Abstract: A multi-layer substrate with metal layers as a moisture diffusion barrier for reduced electrical performance degradation over time after moisture exposure and methods of design and manufacture. The method includes determining a diffusion rate of an insulator material provided between an upper metal layer and an underlying signal line. The method further includes calculating a diffusion distance between a plane opening of the upper metal layer and the underlying signal line using the diffusion rate of the insulator material.

Abstract: A method of manufacturing a transistor comprising providing a substrate, a region of semiconductive material on the substrate, and a region of electrically conductive material on the region of semiconductive material; forming a covering of resist material over said regions; forming a depression in a surface of the covering of resist material that extends over a first portion of said region of conductive material, said first portion separating second and third portions of the conductive region; removing resist material located under said depression to form a window through said covering, exposing said first portion; removing said first portion to expose a connecting portion of the region of semiconductive material that connects the second and third portions; forming a layer of dielectric material over the exposed connecting portion; and forming a layer of electrically conductive material over said layer of dielectric material.

Abstract: A method for fabricating an electronic device includes fixing a rear face of an integrated-circuit chip to a front face of a support wafer. An infused adhesive is applied in the form of drops or segments that are separated from each other. A protective wafer is applied to the infused adhesive, and the infused adhesive is cured. The infused adhesive includes a curable adhesive and solid spacer elements infused in the curable adhesive. A closed intermediate peripheral ring is deposited on the integrated-circuit chip outside the cured infused adhesive, and an encapsulation block is formed such that it surrounds the chip, the protective wafer and the closed intermediate peripheral ring.

Abstract: A light emitting diode (LED) structure including a stacked semiconductor layer, a contact layer and a dielectric reflective layer is provided. The stacked semiconductor layer includes a first type doped layer, a second type doped layer and an active layer disposed between the first type doped layer and the second type doped layer, wherein the first type doped layer, the active layer and the second type doped layer are penetrated by a plurality of recesses. The contact layer is disposed on the second type doped layer. The dielectric reflective layer is disposed on the contact layer and extended into the recesses to connect the contact layer and the first type doped layer with a coverage rate equal to or less than 60% from a top view of the LED structure.

Abstract: A bonding wire includes a wire core including a silver-palladium alloy. A coating layer is disposed on a sidewall of the wire core. A palladium content of the silver-palladium alloy ranges from about 0.1 wt % to about 1.5 wt %.

Abstract: A semiconductor structure capable of real-time spatial sensing of nanoparticles within a nanofluid is provided. The structure includes an array of gate structures. An interlevel dielectric material surrounds the array of gate structures. A vertical inlet channel is located within a portion of the interlevel dielectric material and on one side of the array of gate structures. A vertical outlet channel is located within another portion of the interlevel dielectric material and on another side of the array of gate structures. A horizontal channel that functions as a back gate is in fluid communication with the vertical inlet and outlet channels, and is located beneath the array of gate structures. A back gate dielectric material portion lines exposed surfaces within the vertical inlet channel, the vertical outlet channel and the horizontal channel.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate and a first conductive bump. The semiconductor substrate has an integrated circuit and an interconnection metal layer, and a tilt surface is formed on an edge of the semiconductor substrate. The first conductive bump is electrically connected to the integrated circuit via the interconnection metal layer, and is disposed on the tilt surface, wherein a profile of the first conductive bump extends beyond a side surface of the edge of the semiconductor layer.

Abstract: There is provided a solid-state imaging device including: an imaging pixel including a photoelectric conversion unit which receives incident light; and a phase difference detection pixel including the photoelectric conversion unit and a light shielding unit which shields some of the light incident to the photoelectric conversion unit, in which the imaging pixel further includes a high refractive index film which is formed on the upper side of the photoelectric conversion unit, and the phase difference detection pixel further includes a low refractive index film which is formed on the upper side of the photoelectric conversion unit.

Abstract: A method of manufacturing an organic light-emitting display apparatus includes forming a semiconductor layer on a substrate; forming a gate electrode on the semiconductor layer; forming an interlayer insulating film on an entire surface of the substrate to cover the gate electrode; forming a source electrode and a drain electrode on the interlayer insulating film; and forming a pixel electrode and a pixel-defining film on the source electrode and the drain electrode, wherein the forming of the pixel electrode and the pixel-defining film includes forming the pixel electrode and the pixel-defining film by using one mask.

Abstract: A COA substrate manufacturing method including: forming a TFT on a base substrate; forming a second insulation layer on the TFT; forming a color resist layer on the second insulation layer; forming a third insulation layer on the color resist layer; forming a through hole which exposes the drain electrode of the TFT; forming an ITO film layer on the third insulation layer; forming a photoresist layer on the ITO film layer; performing a light-shielding process to the photoresist layer on the vias-region ITO film layer and an exposure process to the photoresist layer on the non vias-region ITO film layer; developing the photoresist layer on the vias-region ITO and the non vias-region ITO film layers to obtain a photoresist layer plug covered on the vias-region ITO film layer. The photoresist is provided to fill the through hole so as to improve the quality of a display device.

Abstract: A method for forming a semiconductor device includes forming first fins from a first semiconductor material and second fins from a second semiconductor material and encapsulating the first fins and the second fins with a protective dielectric. Semiconductor material between the first fins and the second fins is etched to form trenches. A dielectric fill is employed to fill up the trenches, between the first fins and between the second fins. The first semiconductor material below the first fins and the second semiconductor material below the second fins are oxidized with the first and second fins being protected by the protective dielectric. Fins in an intermediary region between the first fins and the second fins are oxidized to form dummy fins in the intermediary region to maintain a substantially same topology across the device.

Abstract: A triple well isolated diode including a substrate having a first conductivity type and a buried layer in the substrate. The buried layer has a second conductivity type opposite to the first conductivity type. The triple well isolated diode includes an epi-layer over the substrate and the buried layer. A portion of the epi-layer having the first conductivity type contacts the buried layer. The triple well isolated diode includes a first well, a second well, a third well and a deep well in the epi-layer. The first well and the third well have the second conductivity type. The second well and the deep well have the first conductivity type. The second well surrounds sides of the first well. The third well surrounds sides of the second well. The deep well extends beneath the first well to electrically connect to the second well on opposite sides of the first well.

Abstract: A press pack module includes a collector module terminal, an emitter module terminal, a gate module terminal, and an auxiliary module terminal. Each IGBT cassette within the module includes a set of shims, two contact pins, and an IGBT die. The first contact pin provides part of a first electrical connection between the gate module terminal and the IGBT gate pad. The second contact pin provides part of a second electrical connection between the auxiliary module terminal and a shim that in turn contacts the IGBT emitter pad. The electrical connection between the auxiliary emitter terminal and each emitter pad of the many IGBTs is a balanced impedance network. The balanced network is not part of the high current path through the module. By supplying a gate drive signal between the gate and auxiliary emitter terminals, simultaneous IGBT turn off in high speed and high current switching conditions is facilitated.

Abstract: A manufacturing method of a combing bump structure is disclosed. In the manufacturing method, a semiconductor substrate is provided, a pad is formed on the semiconductor substrate, a conductive layer is formed on the pad, a solder bump is formed on the conductive layer, and at least two metal side walls are formed disposed along opposing laterals of the solder bump respectively.

Abstract: There are provided an OLED pixel defining structure, a manufacturing method thereof and an array substrate. The OLED pixel defining structure includes a pixel defining layer, with a plurality of openings corresponding to sub-pixels of different colors being included in the pixel defining layer, each of the openings forming a sub-pixel defining zone of a corresponding color, wherein at least two sub-pixel defining zones of the same color are intercommunicated.