Abstract: A CIS structure is provided, including a translucent structure, a reflective structure surrounding the translucent structure, and a micro lens disposed on a side of the translucent structure. The reflective structure includes a first reflective layer surrounding the translucent structure, a second reflective layer surrounding the first reflective layer, and a third reflective layer surrounding the second reflective layer. The first, second, and third reflective layers respectively have refractive indexes N1, N2, and N3, wherein N1>N2>N3.

Abstract: A FinFET and methods for forming a FinFET are disclosed. A method includes forming a semiconductor fin on a substrate, implanting the semiconductor fin with dopants, and forming a capping layer on a top surface and sidewalls of the semiconductor fin. The method further includes forming a dielectric on the capping layer, and forming a gate electrode on the dielectric.

Abstract: A nonvolatile memory (“NVM”) bitcell with one or more active regions capacitively coupled to the floating gate but that are separated from both the source and the drain. The inclusion of capacitors separated from the source and drain allows for improved control over the voltage of the floating gate. This in turn allows CHEI (or IHEI) to be performed with much higher efficiency than in existing bitcells, thereby the need for a charge pump to provide current to the bitcell, ultimately decreasing the total size of the bitcell. The bitcells may be constructed in pairs, further reducing the space requirements of the each bitcell, thereby mitigating the space requirements of the separate capacitor/s. The bitcell may also be operated by CHEI (or IHEI) and separately by BTBT depending upon the voltages applied at the source, drain, and capacitor/s.

Abstract: A thermoelectric conversion device includes a perovskite film over a substrate and formed with first and second electrodes on the perovskite film, wherein the perovskite film includes a domain having a crystal orientation different from a crystal orientation of a crystal that constitutes the perovskite film.

Abstract: A semiconductor device including source drain stressors is provided. The semiconductor device includes a gate structure including a gate insulating layer and a gate electrode on a semiconductor substrate. Gate spacers may be disposed on sidewalls of the gate structure and a stressor pattern including an impurity region is disposed on a side of the gate structure. The stressor pattern includes a protruded portion having a top surface higher than a bottom surface of the gate structure and a facet in the protruded portion. The facet is slanted at a predetermined angle with respect to an upper surface of the semiconductor substrate and forms a concave portion with one of the gate spacers. A blocking insulating layer may extend conformally on the stressor pattern and the gate spacers and an insulating wing pattern is disposed in the concave portion on the blocking insulating layer.

Abstract: A downsized, highly reliable optical apparatus is stably and easily manufactured with high productivity. The optical apparatus includes: an optical device having a principal surface including an optical unit; a transparent member disposed facing the optical unit; a semiconductor device disposed above a back surface of the optical device and electrically connected to the optical device, the back surface being opposite the principal surface; and a resin member provided in a region adjacent to the optical device and the semiconductor device above a surface of the transparent member, the surface of the transparent member facing the optical device.

Abstract: A method for fabricating a semiconductor apparatus includes forming a variable resistor region, and forming a spacer having a top linewidth and a bottom linewidth substantially equal to each other in the variable resistor region. The forming of the spacer includes forming a first insulating layer in the variable resistor region through a first method, forming a second insulating layer along a surface of the first insulating layer in the variable resistor region through a second method for providing step coverage superior to the first method, and etching the first and second insulating layers.

Abstract: A method for fabricating electronic and photonic devices on a semiconductor substrate using complementary-metal oxide semiconductor (CMOS) technology is disclosed. A substrate is initially patterned to form a first region for accommodating electronic devices and a second region for accommodating photonic devices. The substrate within the first region is thicker than the substrate within the second region. Next, an oxide layer is formed on the substrate. The oxide layer within the first region is thinner than the oxide layer within the second region. A donor wafer is subsequently placed on top of the oxide layer. The donor substrate includes a bulk silicon substrate, a sacrificial layer and a silicon layer. Finally, the bulk silicon substrate and the sacrificial layer are removed from the silicon layer such that the silicon layer remains on the oxide layer.

Abstract: The present disclosure discloses an array substrate, manufacturing method thereof, and display device. The array substrate comprises: a first wiring and a second wiring located in a first metal layer; a first insulating layer covering the first metal layer, wherein the first insulating layer is provided with via holes corresponding to the first wiring and the second wiring respectively; and a jumper located in a second metal layer provided on the first insulating layer, wherein the jumper is connected with the first wiring and the second wiring through the via holes, thereby the first wiring and the second wiring being electrically conducted with each other through the jumper. The array substrate of the present disclosure can be used in liquid crystal television, liquid crystal display, mobile phone, tablet personal computer and other display devices.

Abstract: The present invention provides a film packaging structure for an OLED, an OLED device, and a display apparatus. The film packaging structure for an OLED is an OLED film packaging structure, which includes a flexible film for packaging an OLED unit. The flexible film includes at least one layer of inorganic film, and at least one layer of organic film which is alternately stacked with the at least one layer of inorganic film. Each layer of organic film in the at least one layer of organic film is an integral film, and each layer of inorganic film in the at least one layer of inorganic film includes a plurality of non-connected inorganic film segments. The display apparatus includes the OLED device. The OLED film packaging structure, the OLED device and the display apparatus utilize inorganic films and organic films which are alternately stacked with the inorganic films.

Abstract: The present disclosure provides, in a first aspect, a semiconductor device, including a semiconductor substrate and a gate structure formed over the semiconductor substrate, wherein the gate structure comprises a fin and a ferroelectric high-k material formed at least over sidewall surfaces of the fin. Herein, a first thickness defined by a thickness of the ferroelectric high-k material formed over sidewalls of the fin is substantially greater than a second thickness defined by a thickness of the ferroelectric high-k material formed over an upper surface of the fin.

Abstract: An object is to provide a semiconductor device including an oxide semiconductor, which has stable electrical characteristics and improved reliability. In a transistor including an oxide semiconductor film, insulating films each including a material containing a Group 13 element and oxygen are formed in contact with the oxide semiconductor film, whereby the interfaces with the oxide semiconductor film can be kept in a favorable state. Further, the insulating films each include a region where the proportion of oxygen is higher than that in the stoichiometric composition, so that oxygen is supplied to the oxide semiconductor film; thus, oxygen defects in the oxide semiconductor film can be reduced. Furthermore, the insulating films in contact with the oxide semiconductor film each have a stacked structure so that films each containing aluminum are provided over and under the oxide semiconductor film, whereby entry of water into the oxide semiconductor film can be prevented.

Abstract: Methods for aligning layers more accurately for FinFETs fabrication. An embodiment method includes forming a first pattern in a workpiece using a first photomask, forming a second pattern in the workpiece using a second photomask, the second photomask aligned to the first pattern, and aligning a third pattern to the first and the second patterns by aligning a first feature of the third pattern to a first feature of the first pattern in a first direction, and aligning a second feature of the third pattern to a first feature of the second pattern in a second direction orthogonal to the first direction.

Abstract: Methods for forming integrated graphite-based structures with interconnections between leads and graphene layers are provided. A substrate is patterned to form a plurality of elements on the substrate. A trench separates a first element from an adjacent element in the plurality of elements. A lead is deposited on a side wall of the first element, and a layer from the top of the first element is removed to expose a portion of the lead. Both the deposition of the lead and removal of a layer from the top of the first element are conducted before generation of graphene layers on the top of the first element and the bottom of the trench. Thus, an integrated graphite-based structure having spatially isolated but electrically connected graphene layers is formed.

Abstract: A method of manufacturing a transistor comprising: providing a substrate, a region of semiconductive material supported by the substrate, and a region of electrically conductive material supported by the region of semiconductive material; forming at least one layer of resist material over said regions to form a covering of resist material over said regions; forming a depression in a surface of the covering of resist material, said depression extending over a first portion of said region of conductive material, said first portion separating a second portion of the conductive region from a third portion of the conductive region; removing resist material located under said depression so as to form a window, through said covering, exposing said first portion of the electrically conductive region; removing said first portion to expose a connecting portion of the region of semiconductive material, said connecting portion connecting the second portion to the third portion of the conductive region; forming a layer of

Abstract: Patterned substrates for photovoltaic and other uses are made by pressing a flexible stamp upon a thin layer of resist material, which covers a substrate, such as a wafer. The resist changes phase or becomes flowable, flowing away from locations of impression, revealing the substrate, which is subjected to some shaping process. A typical substrate is silicon, and a typical resist is a wax. Workpiece textures include extended grooves, discrete, spaced apart pits, and combinations and intermediates thereof. Platen or rotary patterning apparatus may be used. Rough and irregular workpiece substrates may be accommodated by extended stamp elements. Resist may be applied first to the workpiece, the stamp, or substantially simultaneously, in discrete locations, or over the entire surface of either. The resist dewets the substrate completely where desired.

Abstract: A super-junction trench MOSFET with closed cell layout having shielded gate is disclosed, wherein closed gate trenches surrounding a deep trench in each unit cell and the shielded gate disposed in the deep trench. Trenched source-body contacts are at least formed between the closed gate trenches and the deep trench. The deep trench has square, rectangular, circle or hexagon shape.

Abstract: A light emitting device includes a p-side heterostructure having a short period superlattice (SPSL) formed of alternating layers of AlxhighGa1-xhighN doped with a p-type dopant and AlxlowGa1-xlowN doped with the p-type dopant, where xlow?xhigh?0.9. Each layer of the SPSL has a thickness of less than or equal to about six bi-layers of AlGaN.

Abstract: A three dimensional multi-die package includes a first die and second die. The first die includes a contact attached to solder. The second die is thinned by adhesively attaching a handler to a top side of the second die and thinning a bottom side of the second die. The second die includes a multilayer contact of layered metallurgy that inhibits transfer of adhesive thereto. The layered metallurgy includes at least one layer that is wettable to the solder. The multilayer contact may include a Nickel layer, a Copper layer upon the Nickel layer, and a Nickel-Iron layer upon the Copper layer. The multilayer contact may also include a Nickel layer, a Copper-Tin layer upon the Nickel layer, and a Tin layer upon the Copper-Tin layer.

Abstract: A micromechanical structure includes a substrate, a micromechanical functional structure, and a conductor track arrangement. The substrate has a top side, and the micromechanical functional structure is formed in the substrate on the top side. The conductor track arrangement is formed above the top side of the substrate, and the conductor track arrangement includes at least two insulation layers of non-conductive material and a conductor track layer of conductive material located between the at least two insulation layers.