Patents Examined by Kevin Parendo
  • Ferroelectric FinFET
    Patent number: 10056376
    Abstract: A semiconductor device includes a semiconductor substrate and a fin positioned above the semiconductor substrate, wherein the fin includes a semiconductor material. Additionally, a ferroelectric high-k spacer covers sidewall surfaces of the fin and a non-ferroelectric high-k material layer covers the ferroelectric high-k spacer and the fin, wherein a portion of the non-ferroelectric high-k material layer is positioned on and in direct contact with the semiconductor material at the upper surface of the fin.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: August 21, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stefan Flachowsky, Ralf Illgen, Jan Hoentschel
  • Capacitor having a graphene structure, semiconductor device including the capacitor and method of forming the same
    Patent number: 10050104
    Abstract: A capacitor includes a first graphene structure having a first plurality of graphene layers. The capacitor further includes a dielectric layer over the first graphene structure. The capacitor further includes a second graphene structure over the dielectric layer, wherein the second graphene structure has a second plurality of graphene layers.
    Type: Grant
    Filed: August 20, 2014
    Date of Patent: August 14, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chewn-Pu Jou, Chih-Hsin Ko, Po-Wen Chiu, Chao-Ching Cheng, Chun-Chieh Lu, Chi-Feng Huang, Huan-Neng Chen, Fu-Lung Hsueh, Clement Hsingjen Wann
  • Salicide formation using a cap layer
    Patent number: 9978604
    Abstract: A method of forming a semiconductor device includes forming a gate stack over a first portion of a source and a first portion of a drain. The method includes depositing a first cap layer comprising silicon over a second portion of the source and depositing a second cap layer comprising silicon over a second portion of the drain. The method includes depositing a metal layer over the gate stack, the first cap layer and the second cap layer. The method includes annealing the semiconductor device until all of the silicon in the first and second cap layers reacts with metal from the metal layer, wherein the annealing causes metal from the metal layer to react with silicon in the first cap layer, the second cap layer, the source, and the drain. Annealing the semiconductor device includes forming a salicide layer having a germanium concentration less than 3% by weight.
    Type: Grant
    Filed: December 3, 2015
    Date of Patent: May 22, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Mei-Hsuan Lin, Chih-Hsun Lin, Ching-Hua Chu, Ling-Sung Wang
  • Uni-directional transient voltage suppressor (TVS)
    Patent number: 9978740
    Abstract: A unidirectional transient voltage suppressor (TVS) device is formed with first and second NPN transistors that are connected in parallel to each other. Each NPN transistor includes a collector region, an emitter. The first and second NPN structures are formed on a common substrate. The first NPN transistor has a floating base and the second NPN transistor has a base shorted to an emitter.
    Type: Grant
    Filed: June 17, 2016
    Date of Patent: May 22, 2018
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Lingpeng Guan, Madhur Bobde, Anup Bhalla
  • Optoelectronic semiconductor device having contact track with relieved thermo-mechanical stress
    Patent number: 9972759
    Abstract: The invention relates to a device (1), comprising at least one optoelectronic semiconductor component (2) and a substrate (5), on which the semiconductor component is arranged, wherein an insulating layer (4) is adjacent to a lateral surface (25) that bounds the semiconductor component; a contact track (6) is arranged on a radiation passage surface of the semiconductor component and is connected to an electrically conductive manner to the semiconductor component; the contact track extends beyond the lateral surface of the semiconductor component and is arranged on the insulating layer; and the contact track is relieved with respect to a thermomechanical load occurring perpendicularly to the lateral surface.
    Type: Grant
    Filed: January 23, 2014
    Date of Patent: May 15, 2018
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Walter Wegleiter, Paola Altieri-Weimar, Juergen Moosburger, Stefan Stegmeier, Karl Weidner
  • Self-enclosed asymmetric interconnect structures
    Patent number: 9960110
    Abstract: Techniques are disclosed that enable improved shorting margin between unlanded conductive interconnect features and neighboring conductive features. The techniques provided are particularly useful, for instance, when lithography registration errors cause neighboring conductive features to be physically closer than expected, but can also he used when such proximity is intentional. In some embodiments, the techniques can be implemented using a layer of electromigration management material (EMM) and one or more insulator layers, wherein the various layers are provisioned to enable a differential etch rate. In particular, the overall etch rate of materials above the target landing pad is faster than the overall etch rate of materials above the off-target landing pad, which results in a self-enclosed conductive interconnect feature having an asymmetric taper or profile.
    Type: Grant
    Filed: December 30, 2011
    Date of Patent: May 1, 2018
    Assignee: INTEL CORPORATION
    Inventor: Boyan Boyanov
  • Removing static electricity from a display device
    Patent number: 9935095
    Abstract: A display device may include a substrate, a display area, a peripheral region, a driving circuit and a dummy wire. A display area formed on a side of the substrate and in which a plurality of pixels are provided. A peripheral region surrounds the display area. A driving circuit provided in the peripheral region, which provides a driving voltage to the plurality of pixels and includes a driving voltage terminal for receiving the driving voltage. A dummy wire portion provided in the peripheral region, separated from the display area with the driving circuit therebetween, and includes a plurality of dummy wires. The driving voltage terminal of the driving circuit is connected to at least one of the plurality of dummy wires.
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: April 3, 2018
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: So Ra Kwon, Jin Suk Park
  • Hybrid interconnect for chip stacking
    Patent number: 9935081
    Abstract: Methods of packaging semiconductor devices and structures thereof are disclosed. In one embodiment, a method of packaging a semiconductor device includes providing a substrate, and adhering a first semiconductor device. Chip stacks are formed by providing a plurality of semiconductor devices and bonding them to the substrate and the first semiconductor device. At least one of the provided semiconductor devices is physically connected to both the substrate and the first semiconductor device it is stack on. Other semiconductor devices may stacked by forming conductive channels in the first semiconductor device, and placing the other semiconductor devices in physical contact with the first semiconductor device and the conductive channels.
    Type: Grant
    Filed: August 20, 2014
    Date of Patent: April 3, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo Lung Pan, Yu-Feng Chen, Chen-Shien Chen, Mirng-Ji Lii
  • Method of positioning elements, particularly optical elements, on the back side of a hybridized-type infrared detector
    Patent number: 9922933
    Abstract: A method of positioning elements or additional technological levels on the incident surface of an infrared detector of hybridized type, said detector being formed of a detection circuit comprising an array network of photosensitive sites for the wavelength ranges of interest, hybridized on a read circuit, said detection circuit resulting from the epitaxial growth of a detection material on a substrate, comprising forming within the detection circuit indexing patterns by marking of the growth substrate.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: March 20, 2018
    Assignee: Societe Francaise De Detecteurs Infrarouges-Sofradir
    Inventors: Olivier Chevrier, Emmanuel Carrere, Nicolas Pere-Laperne
  • TFT with oxide layer on IGZO semiconductor active layer
    Patent number: 9923099
    Abstract: A method for manufacturing a thin-film transistor (TFT) is provided, including the following steps. A gate is formed on a substrate. A gate insulating layer is formed on the gate. A patterned semiconductor layer is formed on the gate insulating layer. A source is formed on the patterned semiconductor layer. The peripheral portion of the source is oxidized to form an oxide layer, wherein the oxide layer covers the source and a portion of the patterned semiconductor layer. A protective layer and hydrogen ions are formed, wherein the protective layer covers the oxide layer and the patterned semiconductor layer. The patterned semiconductor layer not covered by the oxide layer is doped with the hydrogen ions to form a drain. A TFT is also provided.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: March 20, 2018
    Assignee: CHUNGHWA PICTURE TUBES, LTD.
    Inventors: Chin-Tzu Kao, Ya-Ju Lu, Hsiang-Hsien Chung, Wen-Cheng Lu
  • Semiconductor device including a fuse formed on a high thermal conductivity insulating film
    Patent number: 9917054
    Abstract: As means for preventing a leakage of a fuse element cut by laser trimming due to a conductive residue or the like, an insulating film which has a high thermal conductivity and a relatively low adhesion is formed between an element isolation region and the fuse element in the case of forming the fuse element on the element isolation region in a groove on a main surface of an epitaxial substrate. When the fuse element is cut by performing the laser trimming, both of a part of the fuse element and the insulating film below the part of the fuse element are removed.
    Type: Grant
    Filed: November 27, 2014
    Date of Patent: March 13, 2018
    Assignee: Renesas Electronics Corporation
    Inventor: Eisuke Kodama
  • Semiconductor device having stacked chips, a re-distribution layer, and penetration electrodes
    Patent number: 9917066
    Abstract: A lamination structure includes a first semiconductor chip and a second semiconductor chip stacked via a bonding section so that a rear surface of the first semiconductor chip faces the main surface of the second semiconductor chip. At least a part of a side surface of the first semiconductor chip are covered with a first resin, a distribution layer is formed on the plane formed of the main surface of the first semiconductor chip and a surface of the first resin. At least part of electrodes existing in the main surface of the second semiconductor chip is electrically connected to at least part of first external electrodes formed on the distribution layer via the penetration electrodes that penetrate the first semiconductor chip.
    Type: Grant
    Filed: July 16, 2014
    Date of Patent: March 13, 2018
    Assignee: Panasonic Corporation
    Inventors: Nobuo Aoi, Masaru Sasago, Yoshihiro Mori, Takeshi Kawabata, Takashi Yui, Toshio Fujii
  • Method of forming semiconductor packages having through package vias
    Patent number: 9899248
    Abstract: A semiconductor device and method for forming the semiconductor device is provided. The semiconductor device includes an integrated circuit having through vias adjacent to the integrated circuit die, wherein a molding compound is interposed between the integrated circuit die and the through vias. The through vias have a projection extending through a patterned layer and protrude from the patterned layer to expose tapered sidewalls.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: February 20, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Chung-Shi Liu, Chih-Wei Lin, Hung-Jui Kuo, Ming-Da Cheng, Yu-Hsiang Hu
  • Light-emitting device having first and second wiring patterns
    Patent number: 9893038
    Abstract: A light-emitting device includes a base; wiring patterns formed on the base; and light-emitting elements arranged on the base and/or the wiring patterns. The light-emitting elements include: a first group of light-emitting elements that are covered with a first sealing member and constitute a first light-emitting unit, and a second group of light-emitting elements that are covered with a second sealing member and constitute a second light-emitting unit. The wiring patterns include first wiring patterns that drive the first light-emitting unit, and second wiring patterns that drive the second light-emitting unit. The second wiring patterns are separated from each other such that at least one of the first wiring patterns is interposed between adjacent ones of the second wiring patterns. A wire connects said adjacent ones of the second wiring patterns.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: February 13, 2018
    Assignee: NICHIA CORPORATION
    Inventor: Masaki Okubo
  • FinFET transistor with u-shaped channel
    Patent number: 9893191
    Abstract: A semiconductor device having a u-shaped FinFET and methods of forming the same are disclosed. The semiconductor device includes a substrate and a fin over the substrate, wherein the fin has a u-shape from a top view with first and second arm portions and a bridge portion connecting the first and second arm portions. The semiconductor device further includes a first gate over the substrate, engaging the fin at both the first and second arm portions and the bridge portion. A source region of the FinFET is formed in the first arm portion, a drain region of the FinFET is formed in the second arm portion, and a channel region of the FinFET is formed in the fin between the source region and the drain region.
    Type: Grant
    Filed: August 20, 2014
    Date of Patent: February 13, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Yao Wen, Mao-Nan Wang, Sai-Hooi Yeong
  • Semiconductor package having stacked chips and a heat dissipation part and method of fabricating the same
    Patent number: 9875992
    Abstract: An embodiment includes a semiconductor package comprising: a substrate; a first semiconductor chip mounted on the substrate; a second semiconductor chip mounted on a top surface of the first semiconductor chip; a connecting bump disposed between the first and second semiconductor chips to electrically connect the second semiconductor chip to the first semiconductor chip; and a first heat dissipation part disposed on the top surface of the first semiconductor chip between the first and second semiconductor chips and spaced apart from a bottom surface of the second semiconductor chip.
    Type: Grant
    Filed: August 9, 2015
    Date of Patent: January 23, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Junyeong Heo, Chajea Jo, Taeje Cho
  • Asymmetric dense floating gate nonvolatile memory with decoupled capacitor
    Patent number: 9853036
    Abstract: A nonvolatile memory (“NVM”) bitcell with one or more active regions capacitively coupled to the floating gate but that are separated from both the source and the drain. The inclusion of capacitors separated from the source and drain allows for improved control over the voltage of the floating gate. This in turn allows CHEI (or IHEI) to be performed with much higher efficiency than in existing bitcells, thereby the need for a charge pump to provide current to the bitcell, ultimately decreasing the total size of the bitcell. The bitcells may be constructed in pairs, further reducing the space requirements of the each bitcell, thereby mitigating the space requirements of the separate capacitor/s. The bitcell may also be operated by CHEI (or IHEI) and separately by BTBT depending upon the voltages applied at the source, drain, and capacitor/s.
    Type: Grant
    Filed: September 17, 2014
    Date of Patent: December 26, 2017
    Assignee: Synopsys, Inc.
    Inventor: Andrew E. Horch
  • Semiconductor device contact structure having stacked nickel, copper, and tin layers
    Patent number: 9853006
    Abstract: A three dimensional multi-die package includes a first die and second die. The first die includes a contact attached to solder. The second die is thinned by adhesively attaching a handler to a top side of the second die and thinning a bottom side of the second die. The second die includes a multilayer contact of layered metallurgy that inhibits transfer of adhesive thereto. The layered metallurgy includes at least one layer that is wettable to the solder. The multilayer contact may include a Nickel layer, a Copper layer upon the Nickel layer, and a Nickel-Iron layer upon the Copper layer. The multilayer contact may also include a Nickel layer, a Copper-Tin layer upon the Nickel layer, and a Tin layer upon the Copper-Tin layer.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: December 26, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Charles L. Arvin, Harry D. Cox, Eric D. Perfecto, Thomas A. Wassick
  • Method of making a stacked device assembly
    Patent number: 9847248
    Abstract: Multiple devices, including a first device and a second device, have operational circuitry and opposing first and second surfaces. First and second electrical contacts are formed at the first surface, while a third electrical contact is formed at the second surface opposite the first electrical contact. The first electrical contact is electrically connected to the operational circuitry, and the second electrical contact is electrically connected to the third electrical contact. The first device and the second device are subsequently stacked such that the first surface of the second device is located adjacent the second surface of the first device such that the first electrical contact of the second device is aligned with the third electrical contact of the first device. The first electrical contact of the second device is electrically connected to the third electrical contact of the first device.
    Type: Grant
    Filed: May 7, 2014
    Date of Patent: December 19, 2017
    Assignee: Rambus Inc.
    Inventors: Frederick A. Ware, Ely K. Tsern, Ian P. Shaeffer
  • Semiconductor device having an oxide semiconductor film and a metal oxide film
    Patent number: 9842937
    Abstract: The oxide semiconductor film has the top and bottom surface portions each provided with a metal oxide film containing a constituent similar to that of the oxide semiconductor film. An insulating film containing a different constituent from the metal oxide film and the oxide semiconductor film is further formed in contact with a surface of the metal oxide film, which is opposite to the surface in contact with the oxide semiconductor film. The oxide semiconductor film used for the active layer of the transistor is an oxide semiconductor film highly purified to be electrically i-type (intrinsic) by removing impurities such as hydrogen, moisture, a hydroxyl group, and hydride from the oxide semiconductor and supplying oxygen which is a major constituent of the oxide semiconductor and is simultaneously reduced in a step of removing impurities.
    Type: Grant
    Filed: June 9, 2015
    Date of Patent: December 12, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki