Patents Examined by Kevin Parendo
  • Light emitting device with packaging having an adhesive in a groove for attaching a transparent cover
    Patent number: 9831395
    Abstract: A light emitting device includes a body having a cavity and a step difference structure around the cavity, a plurality of electrodes in the cavity, a light emitting chip in the cavity, a transparent window having an outer portion provided on the step difference structure to cover the cavity, and an adhesive member between the transparent window and the body. The adhesive member includes a first adhesive member between an outer bottom surface of the transparent window and a bottom of the step difference structure and a second adhesive member between the outer portion of the transparent window and the body.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: November 28, 2017
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Baek Jun Kim, Hiroshi Kodaira, Ki Man Kang, Ha Na Kim, Hyun Don Song, Jung Woo Lee, Jung Hun Oh
  • Thin film transistor array panel having an oxide semiconductor including silicon
    Patent number: 9828666
    Abstract: An exemplary embodiment provides a thin film transistor array panel, including: a substrate; an oxide semiconductor layer disposed on the substrate; an insulating layer disposed on the oxide semiconductor layer; and a pixel electrode disposed on the insulating layer. The oxide semiconductor layer includes a first layer and a second layer disposed on the first layer, the second layer includes an oxide semiconductor including silicon, and the second layer contacts the insulating layer.
    Type: Grant
    Filed: August 19, 2014
    Date of Patent: November 28, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Hyoung-Rae Lee, Moon Ju Kim, Eun Suk Kim, Seok-Kun Yoon, Kwang Youl Lee, Jong-Won Choo
  • Chip stack cooling structure
    Patent number: 9818726
    Abstract: An apparatus comprises a first die, a thermal cooler formed over at least a portion of the first die, a second die formed over at least a portion of the thermal cooler, and a plurality of through-silicon vias providing electrical connections between the first die and the second die. The thermal cooler comprises a plurality of fluid channels for fluid cooling of the first die and the second die, the plurality of fluid channels being formed horizontally through the thermal cooler. The plurality of through-silicon vias are formed vertically through the first die, the thermal cooler and the second die.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: November 14, 2017
    Assignee: International Business Machines Corporation
    Inventor: Timothy J. Chainer
  • Stacked electronic device including a protective wafer bonded to a chip by an infused adhesive
    Patent number: 9773740
    Abstract: A method for fabricating an electronic device, and an electronic device in a stacked configuration, includes a rear face of an integrated-circuit chip that is fixed to a front face of a support wafer. A protective wafer is located facing and at a distance from the front face of the chip, and an infused adhesive is interposed between the chip and the protective wafer and located on a zone of the front face of the chip outside a central region of this front face. The infused adhesive includes a curable adhesive and solid spacer elements infused in the curable adhesive. An obstruction barrier is arranged between the chip and the protective wafer and is disposed outside the central region of the front face of the chip. An encapsulation ring surrounds the chip, the protective wafer and the obstruction barrier.
    Type: Grant
    Filed: August 10, 2015
    Date of Patent: September 26, 2017
    Assignee: STMICROELECTRONICS (GRENOBLE 2) SAS
    Inventors: Karine Saxod, Marika Sorrieul
  • Semiconductor device having a wide-gap semiconductor layer in an insulating trench
    Patent number: 9761588
    Abstract: A conventional DRAM needs to be refreshed at an interval of several tens of milliseconds to hold data, which results in large power consumption. In addition, a transistor therein is frequently turned on and off; thus, deterioration of the transistor is also a problem. These problems become significant as the memory capacity increases and transistor miniaturization advances. A transistor is provided which includes a wide-gap semiconductor and has a trench structure including a trench for a gate electrode and a trench for element isolation. Even when the distance between a source electrode and a drain electrode is decreased, the occurrence of a short-channel effect can be suppressed by setting the depth of the trench for the gate electrode as appropriate.
    Type: Grant
    Filed: October 26, 2015
    Date of Patent: September 12, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hiromichi Godo
  • Final passivation for wafer level warpage and ULK stress reduction
    Patent number: 9754905
    Abstract: Embodiments are directed to a method of forming a semiconductor chip package and resulting structures having an annular PSPI region formed under a BLM pad. An annular region is formed under a barrier layer metallurgy (BLM) pad. The annular region includes a photosensitive polyimide (PSPI). A conductive pedestal is formed on a surface of the BLM pad and a solder bump is formed on a surface of the conductive pedestal. The annular PSPI region reduces wafer warpage and ULK peeling stress.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: September 5, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ekta Misra, Krishna R. Tunga
  • Lateral double-diffused MOS transistor having deeper drain region than source region
    Patent number: 9741844
    Abstract: Provided is a semiconductor power device. The semiconductor power device includes a well disposed in a substrate, a gate overlapping the well, a source region disposed at one side of the gate, a buried layer disposed in the well, and a drain region or a drift region contacting the buried layer.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: August 22, 2017
    Assignee: Magnachip Semiconductor, Ltd.
    Inventors: Young Bae Kim, Jin Woo Moon, Francois Hebert
  • Nanofluid sensor with real-time spatial sensing
    Patent number: 9733210
    Abstract: A semiconductor structure capable of real-time spatial sensing of nanoparticles within a nanofluid is provided. The structure includes an array of gate structures. An interlevel dielectric material surrounds the array of gate structures. A vertical inlet channel is located within a portion of the interlevel dielectric material and on one side of the array of gate structures. A vertical outlet channel is located within another portion of the interlevel dielectric material and on another side of the array of gate structures. A horizontal channel that functions as a back gate is in fluid communication with the vertical inlet and outlet channels, and is located beneath the array of gate structures. A back gate dielectric material portion lines exposed surfaces within the vertical inlet channel, the vertical outlet channel and the horizontal channel.
    Type: Grant
    Filed: December 31, 2014
    Date of Patent: August 15, 2017
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Ali Khakifirooz, Ghavam G. Shahidi, Davood Shahrjerdi
  • Display device including a COA substrate having a photoresist plug on an ITO film
    Patent number: 9726956
    Abstract: A COA substrate manufacturing method including: forming a TFT on a base substrate; forming a second insulation layer on the TFT; forming a color resist layer on the second insulation layer; forming a third insulation layer on the color resist layer; forming a through hole which reveals the drain electrode of the TFT; forming an ITO film layer on the third insulation layer; forming a photoresist layer on the ITO film layer; performing a light-shielding process to the photoresist layer on the vias-region ITO film layer and an exposure process to the photoresist layer on the non vias-region ITO film layer; developing the photoresist layer on the vias-region ITO and the non vias-region ITO film layers to obtain a photoresist layer plug covered on the vias-region ITO film layer. The present invention utilizes the photoresist to fill the through hole which can improve the quality of a display device.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: August 8, 2017
    Assignee: Shenzhen China Star Optoelectronics Technology Co., Ltd
    Inventor: Yue Wu
  • Manufacturing method of semiconductor device with silicon layer containing carbon
    Patent number: 9722044
    Abstract: A semiconductor device having an n channel MISFET formed on an SOI substrate including a support substrate, an insulating layer formed on the support substrate and a silicon layer formed on the insulating layer has the following structure. An impurity region for threshold adjustment is provided in the support substrate of a gate electrode so that the silicon layer contains carbon. The threshold value can be adjusted by the semiconductor region for threshold adjustment in this manner. Further, by providing the silicon layer containing carbon, even when the impurity of the semiconductor region for threshold adjustment is diffused to the silicon layer across the insulating layer, the impurity is inactivated by the carbon implanted into the silicon layer. As a result, the fluctuation of the transistor characteristics, for example, the fluctuation of the threshold voltage of the MISFET can be reduced.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: August 1, 2017
    Assignee: Renesas Electronics Corporation
    Inventors: Takaaki Tsunomura, Toshiaki Iwamatsu
  • Semiconductor device having multiple bonded heat sinks
    Patent number: 9721866
    Abstract: A method for manufacturing a semiconductor device is provided, the method including: mounting a first element on a wiring substrate, placing a first heat sink on the first element with a metal material interposed between the first heat sink and the first element, attaching the first heat sink to the first element via the metal material by heating and melting the metal material, and mounting a second element on the wiring substrate after the steps of attaching the first heat sink to the first element.
    Type: Grant
    Filed: November 18, 2015
    Date of Patent: August 1, 2017
    Assignee: SOCIONEXT INC.
    Inventors: Takeshi Imamura, Nobutaka Shimizu, Yasunori Fujimoto
  • Semiconductor unit with proection circuit and electronic apparatus
    Patent number: 9711497
    Abstract: A semiconductor unit includes: a transistor configured to provide electrical conduction between a first terminal and a second terminal, based on a trigger signal; and a trigger device formed in a transistor region where the transistor is formed, and configured to generate the trigger signal, based on a voltage applied to the first terminal.
    Type: Grant
    Filed: May 7, 2014
    Date of Patent: July 18, 2017
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventor: Katsuhiko Fukasaku
  • Method of manufacturing a three dimensional integrated circuit by transfer of a mono-crystalline layer
    Patent number: 9711407
    Abstract: A semiconductor device includes a first mono-crystallized layer including first transistors, and a first metal layer forming at least a portion of connections between the first transistors; and a second layer including second transistors, the second transistors including mono-crystalline material, the second layer overlying the first metal layer, wherein the first metal layer includes aluminum or copper, and wherein the second layer is less than one micron in thickness and includes logic cells.
    Type: Grant
    Filed: December 16, 2010
    Date of Patent: July 18, 2017
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist, Israel Beinglass, J. L. de Jong, Deepak C. Sekar, Paul Lim
  • Dual side solder resist layers for coreless packages and packages with an embedded interconnect bridge and their methods of fabrication
    Patent number: 9704735
    Abstract: A coreless package substrate with dual side solder resist layers is disclosed. The coreless package substrate has a top side and a bottom side opposite of the top side and includes a single build-up structure formed of at least one insulating layer, at least one via, and at least one conductive layer. The coreless package substrate also includes a bottom plurality of contact pads on the bottom side, and a top plurality of contact pads on the top side. A bottom solder resist layer is on the bottom side, and a top solder resist layer is on the top side. The concept of dual side solder resist is extended to packages with interconnect bridge with C4 interconnection pitch over a wide range.
    Type: Grant
    Filed: August 19, 2014
    Date of Patent: July 11, 2017
    Assignee: Intel Corporation
    Inventors: Manohar S. Konchady, Tao Wu, Mihir K. Roy, Wei-Lun K. Jen, Yi Li
  • Interposer frame and method of manufacturing the same
    Patent number: 9691636
    Abstract: The mechanisms of using an interposer frame to form a PoP package are provided in the disclosure. The interposer frame is formed by using a substrate with one or more additives to adjust the properties of the substrate. The interposer frame has openings lined with conductive layer to form through substrate vias (TSVs) with solder balls on adjacent packages. The interposer frame enables the reduction of pitch of TSVs, mismatch of coefficients of thermal expansion (CTEs), shorting, and delamination of solder joints, and improve mechanical strength of the package.
    Type: Grant
    Filed: March 28, 2012
    Date of Patent: June 27, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Jiun Yi Wu
  • Display device having vertical oxide semiconductor channel layer on sidewall of insulating spacer
    Patent number: 9679922
    Abstract: A display device includes a substrate, a first insulating layer having a first side wall, an oxide semiconductor layer on the first side wall, a gate electrode facing the oxide semiconductor layer, a gate insulating layer between the oxide semiconductor layer and the gate electrode, a first transparent conductive layer between the oxide semiconductor layer and the substrate, the first transparent conductive layer being connected with a first portion of the oxide semiconductor layer, a first electrode on the first insulating layer on the side opposite to the substrate, the first electrode being connected with a second portion of the oxide semiconductor layer, and a second transparent conductive layer connected with the first transparent conductive layer, the second transparent conductive layer forming the same layer with the first transparent conductive layer.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: June 13, 2017
    Assignee: Japan Display Inc.
    Inventor: Toshinari Sasaki
  • Method for manufacturing a fin MOS transistor
    Patent number: 9673329
    Abstract: A fin MOS transistor is made from an SOI-type structure that includes a semiconductor layer on a silicon oxide layer coating a semiconductor support. A trench formed from the surface of the semiconductor layer delimits at least one fin in the semiconductor layer, that trench extending at least to an upper surface of the semiconductor support. Etched recesses in sides of a portion of the silicon oxide layer located under the fin are filled with a material selectively etchable over silicon oxide.
    Type: Grant
    Filed: December 4, 2015
    Date of Patent: June 6, 2017
    Assignees: STMicroelectronics SA, Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Yves Morand, Romain Wacquez, Laurent Grenouillet, Yannick Le Tiec, Maud Vinet
  • Memory structure having material layer made from a transition metal on interlayer dielectric
    Patent number: 9666797
    Abstract: A memory structure and a manufacturing method for the same are disclosed. The memory structure comprises a lower electrode, an upper insulating layer, a material layer, a dielectric film, and an upper electrode. The upper insulating layer is on the lower electrode. The material layer is on the upper insulating layer. The upper insulating layer and the material layer have a common opening to expose a portion of the lower electrode. The dielectric film is on the exposed portion of the lower electrode. The dielectric film and the material layer contain a same first transition metal. The upper electrode is on the dielectric film and fills the common opening.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: May 30, 2017
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Feng-Min Lee, Yu-Yu Lin
  • Method of manufacturing a semiconductor device including removing a relief layer from back surface of semiconductor chip
    Patent number: 9646856
    Abstract: A method of manufacturing a device includes providing a semiconductor chip having a first face and a second face opposite to the first face with a contact pad arranged on the first face. The semiconductor chip is placed on a carrier with the first face facing the carrier. The semiconductor chip is encapsulated with an encapsulation material. The carrier is removed and the semiconductor material is removed from the second face of the first semiconductor chip without removing encapsulation material at the same time.
    Type: Grant
    Filed: May 19, 2015
    Date of Patent: May 9, 2017
    Assignee: Intel Deutschland GmbH
    Inventors: Thorsten Meyer, Klaus Reingruber, David O'Sullivan
  • Tuning tensile strain on FinFET
    Patent number: 9627385
    Abstract: A fin field effect transistor (FinFET) having a tunable tensile strain and an embodiment method of tuning tensile strain in an integrated circuit are provided. The method includes forming a source/drain region on opposing sides of a gate region in a fin, forming spacers over the fin, the spacers adjacent to the source/drain regions, depositing a dielectric between the spacers; and performing an annealing process to contract the dielectric, the dielectric contraction deforming the spacers, the spacer deformation enlarging the gate region in the fin.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: April 18, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Zhi-Chang Lin, Guan-Lin Chen, Ting-Hung Hsu, Jiun-Jia Huang