Abstract: The present invention relates to an improve method for forming a UBM pad and solder bump connection for a flip chip which eliminates at least two mask steps required in standard UBM pad forming processes when repatterning the bond pad locations.

Abstract: A method of fabricating a bonding pad window, includes providing a substrate, which is metallized with a first metallization layer; forming a dielectric layer over the first metallization layer; defining the dielectric layer with a first mask to form a via; forming a plug in the via; forming a second metallization layer over the plug and the dielectric layer; patterning the second metallization layer to expose the dielectric layer; forming a passivation layer over the second metallization layer; and defining the passivation layer with the first mask to form the bonding pad window. This improves and simplifies the formation of a bonding pad window. For example, the process of forming a mask, which is used to form the bonding pad window, can be omitted. The previous via mask is used to form the bonding pad window and the internal circuit probing window at the same time.

Abstract: An improved method of attaching a semiconductor chip onto a die pad of a lead frame using an epoxy adhesive by dispensing the epoxy adhesive onto the die pad, decreasing a viscosity of the epoxy adhesive dispensed onto the die pad by blowing a hot gas over at least part of the epoxy adhesive thereby preventing a formation of an epoxy tail, and placing the chip into the adhesive to attach the chip to the die pad. The hot gas used may be air or nitrogen, having a temperature from 50.degree. C. to 70.degree. C. The hot gas is blown from a blower between the die pad and the dispenser, and may be blown onto the epoxy adhesive from more than one direction.

Abstract: An electrically conductive apparatus includes a) an electrically non-conducting substrate, the substrate having a base surface and an adjacent elevated surface, the elevated surface being spaced from the base surface by a first distance thereby defining a step having a step wall; b) a capping layer of first electrically conductive material coating the elevated surface only portions of the step wall, the capping layer having outer top and outer side portions; and c) a conductive trace of second electrically conductive material which is different from the first electrically conductive material; the conductive trace overlying the substrate, portions of the step wall not covered by the capping layer, and the outer side portions of the capping layer. Methods are disclosed for producing such a construction, for forming an electrically conductive projection outwardly extending from a substrate, and for providing an electrical interconnection between adjacent different elevation areas on a substrate.

Abstract: This circuit comprises an insulating substrate covered on at least part of its surface by a fine conducting layer (7) whose geometrical form corresponds to the layout chosen for the circuit; the said conducting layer having one or more very fine grooves (9) with a depth of more than 1 .mu.

Abstract: A method of applying adhesives to leads of lead frame, a nozzle of a dispenser is moved horizontally above one lead and positioned against the lead at a predetermined distance. While keeping adhesives flowing from the nozzle of the dispenser, the dispenser is moved horizontally relative to the leads in a direction from one lead to the next lead so that the distance is kept constant. Then the adhesives are applied to a predetermined portion of each lead. When the application of adhesives to the last lead is complete, the nozzle is raised and moved horizontally. Therefore, the number of upward and downward movements of the nozzle is greatly reduced and the application time can be shortened. Preferably, the distance between the tip of the nozzle and the surface of the lead is to be one-fourth to three times as long as the inside diameter of the nozzle.

Abstract: An electrode-pin forming mask is used to form electrode pins on the semiconductor chip. The electrode-pin forming mask has electrode-pin forming holes matching electrode pads previously formed on the semiconductor chip. A screen-printing technique is used to form the electrode pins on the semiconductor chip through the electrode-pin forming mask. That is, conductive material in a paste state is pushed into the electrode-pin forming holes in a condition where the electrode-pin forming mask has been placed on the semiconductor chip and positions of the electrode-pin forming holes match positions of the electrode pads of the semiconductor chip, respectively. The conductor material thus pushed into the electrode-pin forming holes is thus shaped as to form the electrode pins projecting from the electrode pads of the semiconductor chip.

Abstract: Methods for packaging TAB-BGA integrated circuits are disclosed, which mainly include steps of providing a double-sided polyimide; forming first dry film layers; sequentially performing a multi-layer electroplating operation of electro-coppering, electronickelling, gold plating and electronickelling again (or electronickelling and gold plating, or electro-coppering and electronickelling); removing the first dry film layers; serving a lower second dry film layer as a mask for etching a bottom thin copper layer to define a plurality of predetermined openings; serving the bottom thin copper layer as a mask for applying a laser etching operation to the polyimide substrate to define holes without totally penetrating the polyimide substrate; applying an electrolytic plating operation to the holes for forming protruding contacts; etching the exposed top thin copper layer and/or removing a nickel-electroplated layer; and respectively defining a chip installation hole and a plurality of through holes by performing a l

Abstract: A TAB Grid Array (TGA) package allows automated assembly using established manufacturing equipment similar to those used in the production of plastic ball grid Array (PBGA) package assembly. The TGA package are formed, using as starting material, a metal strip having the same critical dimensions and tooling holes as those used for a PBGA package. In this invention, the stiffener is designed to serve as a carrier throughout the assembly of the TGA package. The wire bonded TGA cavity package, including the solder balls, is first fully assembled prior to the attachment of the semiconductor die. Subsequently, the semiconductor die is attached to the stiffener, wires are bonded between the semiconductor die and the tape frame, and the entire assembly is encapsulated. The process of the present invention provides a high device assembly yield usually not achievable by the PBGA packages.

Abstract: A first camera detects a positional relationship among first, second and third nozzles. A second camera detects pick-up positions of chips in parts feeders. Tolerance zones for the respective chips are determined, within which the nozzle can pick up the chip. When one of nozzles is placed in the corresponding pick-up position, it is judged whether or not other nozzles are located within the corresponding tolerance zones, respectively. If the judgment result is "YES", the nozzles pick up the chips simultaneously , and if this result is "NO", the nozzles pick up the chips separately.

Abstract: A lead frame for use with a plastic encapsulated semiconductor device includes a tab on which the semiconductor chip is mounted, chip pad supporting leads, inner leads to be electrically coupled with the semiconductor chip, outer leads formed in a monoblock structure together with the inner leads, and a frame for supporting the chip pad supporting leads and outer leads. In the lead frame, there is disposed a dam member only between the outer leads. Alternatively, dummy outer leads are formed between the frame and leads adjacent thereto so as to connect the dummy leads to the outer leads by the dam member. The frame is removed after the semiconductor device is assembled.

Abstract: General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.

Abstract: An integrated circuit heat transfer element (6,30) is made by selecting thermally conductive fibers having aspect ratios of length to diameter of more than 1, selecting a resin and combining the fibers and the resin to create a formable resin/fiber compound. The resin/fiber compound is formed into a composite material in part by applying pressure to the formable resin/fiber compound, which aligns the fibers, and when cured creates a thermally anisotropic composite material to maximize heat conduction along the aligned fibers. The thermally anisotropic composite material has a coefficient of thermal expansion (CTE) of less than about 10.times.10.sup.-6 cm/cm/.degree. C. The composite material has a thermal conductivity in the direction of the carbon fibers of at least 50 W/m.degree. K. The IC device is preferably secured to the heat transfer element using a thermally conductive adhesive.

Abstract: A component having a movable micro mechanical function element arranged in a cavity having a cover layer supported by webs or pillar-like supports is provided. The movable element is potentially covered with a termination layer for closing the etching holes present in the cover layer. Electrical terminals of the movable part, the cover layer and doped regions produced in the substrate as a cooperating electrode enable the realization of an acceleration sensor that is easy to mount in a housing.

Abstract: A pad electrode is formed on a main surface of a semiconductor chip. A passivation film, which covers a surface portion of the pad electrode, is formed on the main surface of the semiconductor chip. An internal connection conductor is formed on a surface portion of the pad electrode. The semiconductor chip is covered with a molding resin which exposes only a top surface of the internal connection conductor. An external connection conductor is formed on a top surface of the internal connection conductor. The external connection conductor has a substantially flat top surface. Thereby, a plastic molded semiconductor package can be easily mounted on a printed board, and can have improved reliability after being joined on the printed board.

Abstract: A method for inspecting and testing IC flip-chips without removing the chips from their packages includes providing at least three alignment holes on a substrate surface of the chip opposite its circuit-patterned face. The alignment indicia are positioned in a predetermined relationship to the circuit pattern, and provide marks for aligning a mirror image of a circuit pattern of the circuit-patterned face as an overlay on the substrate side. The substrate can be thinned in a region corresponding to the circuit pattern to enhance the accessibility of the circuit-patterned side via the substrate.

Abstract: A method for the removal of voids and gas bubbles within uncured or partially cured microelectronic component encapsulants and adhesive/chip attach layers. A sealed void or gas bubble within a gap between a microelectronic component and a supporting substrate is substantially eliminated through the application of a uniform pressure (isostatic or hydrostatic) and energy such that a substantially void/bubble free interposer layer is created.

Abstract: A method of fabricating a field effect thin film transistor is provided, in which, after a first amorphous semiconductor layer having a predetermined thickness is deposited on a gate insulating film, the first amorphous semiconductor layer is transformed to a micro-crystal semiconductor layer by exposing it to hydrogen plasma produced by hydrogen discharge and, then, a second amorphous semiconductor layer is deposited on the micro-crystal semiconductor layer. According to this method, it is possible to fabricate a high performance and high quality field effect thin film transistor through a simplified step of forming the micro-crystal semiconductor which becomes a channel region thereof.

Abstract: A method of encapsulating a dielectric. According to the method of the present invention, a disposable post is formed over a portion of a substrate. Next, a first dielectric layer is formed over the substrate and the disposable post. A second dielectric layer is then formed over the first dielectric layer. Next, a third dielectric layer is formed over the second dielectric layer. A portion of the third dielectric layer is then removed so as to reveal the disposable post. The disposable post is then removed to form an opening.

Abstract: A method for forming a semiconductor device comprises the steps of providing a semiconductor die having a plurality of pads thereon with at least one bond wire electrically coupled with one of the pads and providing a holder having a cavity therein. The die is placed in the cavity, then a layer of encapsulation is formed within the cavity to cover the die. Subsequently, the encapsulated die is removed from the cavity.