Abstract: A method of making a leadframe and a semiconductor device using the leadframe. The leadframe has a plurality of outer leads. Linking isolation members are located in the direction crossing to the extension direction of the outer leads so as to connect the neighboring outer leads with each other.

Abstract: A method and apparatus for electrically insulating heat sinks in electronic power devices that includes the formation of an insulating layer on the face of the electronic device having the heat sink. The insulating layer may be formed from an epoxy resin, commonly known as "solder mask" in the manufacture of printed circuits.

Abstract: A method of assembly an integrated circuit die to a heat sink by first providing a lead frame that has a die-attach paddle portion having a top surface, a bottom surface, and an opening therethrough, positioning a heat sink having a raised portion on its top surface abutting the bottom surface of the die-attach paddle portion, and then frictionally engaging the heat sink and the die-attach paddle together and bonding an integrated circuit chip to the top surface of the heat sink with an adhesive material sandwiched therein between such that the assembly can be placed in a mold apparatus for forming a plastic encapsulated package.

Abstract: Crack stops for substantially preventing cracks and chips produced along the dicing channel from spreading into the active areas of the ICs are described. The crack stops are formed by creating discontinuities in the thickness of the dielectric layer in the dicing channel near the chip edges. The discontinuities can result in increasing and/or decreasing the thickness of the dielectric layer.

Abstract: A method for forming a chip module such as a multi chip module or a memory module is provided. The multi chip module includes a substrate configured to mount a plurality of semiconductor dice thereon. The substrate includes raised contact members formed in patterns that correspond to the locations of bond pads on the dice. An anisotropic conductive adhesive layer is formed between the contact members on the substrate and the bond pads on the dice to secure the dice to the substrate and form an electrical connection therebetween. In addition, an underfill layer can be formed between the dice and substrate to fill the gap therebetween and further secure the dice to the substrate. Conductors and input/output pads formed on the substrate form electrical paths to and from the contact members. To form a memory module, one or more multi chip modules can be mounted to a supporting substrate having an edge connector in electrical communication with the conductors and with contact members on the substrates.

Abstract: A method of separating electronic devices contained in a carrier which are provided at the surface of the carrier and are covered by a protective layer. Openings are provided above separation regions between adjacent electronic devices. The material of the carrier is removed in the separation regions starting from the openings, and the electronic devices are, at least during the material-removing process, confined in the carrier by respective regions with a material removal property different from that of the carrier.

Abstract: A process of laminating a large-layer-count (LLC) substrates includes formation of first and second vias through respective substrates. A conductive path is formed through each of the respective vias, and posts are formed on the respective vias, electrically connected to the respective conductive path. A non-flowable adhesive layer having an aperture is provided between the LLC substrates so that the posts confront each other through the aperture. The LLC substrates are pressed together through the non-flowable adhesive layer to mechanically bond them together, and so that the posts abut each other. Simultaneously, the posts are electrically bonded to each other in the aperture.

Abstract: A flat-panel field emission display comprises a luminescent faceplate, a rigid backplate, and an interposed or sandwiched emitter or cathode plate. A dielectric connector ridge is screen-printed over the faceplate's rear surface. Upper and lower level conductors are then screen printed over the faceplate. The lower-level conductors are applied directly on the faceplate rear surface. The upper-level conductors are applied atop the connector ridge. A plurality of bond wire interconnections extend between individual screen-printed conductors of the upper and lower levels. The bond wire interconnections create inter-level electrical interconnections between said individual screen-printed conductors. The cathode plate is positioned over the connector ridge. The cathode plate has a plurality of die bond pads facing the faceplate rear surface and aligned with the upper-level conductors.

Abstract: A hermetically sealed ceramic integrated circuit package and method for achieving same, the package including an internal lead frame attached to an integrated circuit die in a lead-on-chip configuration, an external lead frame attached to the package exterior in a lead-on-package configuration and a high temperature adhesive layer which attaches the internal lead frame to the integrated circuit die.

Abstract: The semiconductor device disclosed has a cap in which, at an undersurface periphery portion, a plurality of looped projections are formed for intercepting a continuous bubble path that may be formed for a gas to escape. The preparatory stage steps of assembling the device includes forming a plated layer on a lead frame, adhesively fixing the lead frame on a base plate, cutting and separating leads from the lead frame, and shaping the leads into a predetermined form. The assembling stage steps of the device includes mounting a semiconductor chip on the base plate and bonding electrodes on the semiconductor chip and the leads, and mounting the cap which has the looped projections for intercepting a continuous bubble path that may be formed for a gas to escape. Since the steps such as forming a plated layer and shaping the leads have been completed in the preparatory stage, the assembling steps which include the mounting of the cap having the looped projections can be efficiently carried out.

Abstract: The specification describes an interconnection technique using compliant metal coated photodefined polymer bumps for mounting and interconnecting component assemblies on substrates such as glass, printed wiring boards, etc. The polymer chosen for the bump structure has a relatively low T.sub.g and the polymer bump is metallized in a way that substantially encapsulates the polymer.

Abstract: The present invention is premised on a semiconductor device in which one semiconductor chip is mounted on each of both faces of a die pad of a lead frame. The semiconductor chips are disposed such that the projected lines, on the die pad, of the corresponding sides of the semiconductor chips, intersect with each other at an angle of 45.degree.. The tips of inner leads are located in the sides of a virtual octagon formed by outwardly enlarging an octagon formed by connecting, to one another, the apexes of the semiconductor chips. The sides of the virtual octagon are respectively opposite to the sides of the semiconductor chips. The number of the inner leads of which tips are located in each of the sides of the virtual octagon, is the same as the number of bonding pads disposed at each of the sides of the semiconductor chips.

Abstract: A semiconductor device (10) includes a semiconductor substrate (11) underlying an oxide layer (12). A layer (13) comprised of titanium overlies the oxide layer (12). The oxide layer (12) improves the adhesion of the layer (13) comprised of titanium to the semiconductor substrate (11).

Abstract: An insulating layer 6 is formed covering a lower level wiring layer 5. Contact hole 11 registered with the lower level wiring 5 is then formed in the insulating layer 6. An adhesion layer 12 is sputtered on the lower level wiring layer 5 and a whole surface of the third level insulating layer 6. Then, a blanket tungsten layer 13 is deposited on the adhesion layer 12. The whole surface of the blanket tungsten layer 13 is etched back until a small hollow gap is formed at the upper end portion of the contact hole 11, to leave the blanket tungsten layer 13 only in the inside of the contact hole 11. Thereafter, an Al alloy layer is reflow-sputtered on the whole surface of the insulating layer 6 and the inside of the contact holes at a comparatively low temperature to form an upper level wiring layer 15. The surface unevenness produced in etch-back process can be planarized. A wiring having a good coverage, a good quality of layer, and a flat surface can be formed.

Abstract: This process comprises the following steps:a) make a set of chips (110, 111, 112, 113) on a substrate (100), each chip including a number of electrodes (110a, 110b, 111a, 111b),b) individual validity test on each chip and the formation of at least one electrical network (117a, 117b) for addressable matched electrodes on different valid chips,c) make a deposit successively on matched electrode sets by dipping the substrate in an appropriate electrochemical bath and by application of appropriate voltages on the electrical network to cause an electrochemical reaction on the electrodes.

Abstract: A three dimensional flexible assembly of integrated circuits and method of fabricating the assembly of circuits including a folded flexible substrate with integrated circuit chips. The invention has provisions for allowing mechanical and electrically functional attachment of integrated circuit chips to one or both sides of the flexible substrate using flip chip assembly techniques. In addition, a rigid package substrate is provided upon which the folded substrate is secured with the associated chips. The chips are electrically connected to the flexible substrate and the flexible substrate is in turn electrically connected to the rigid substrate. A cover is also provided that covers and protects the flexible substrate and the associated chips as well as a portion of the connected rigid package substrate. In an additional embodiment, the cover and rigid substrate are omitted and instead the combined folded flexible substrate and integrated circuit chips are encapsulated with a suitable compound.

Abstract: A semiconductor package substrate (10) has an array of package sites (13,14,16,21,22, and 23) that are substantially identical. The entire array of package sites (13,14,16,21,22, and 23) is covered by an encapsulant (19). The individual package sites (13,14,16,21,22, and 23) are singulated by sawing through the encapsulant (19) and the underlying semiconductor package substrate (10).

Abstract: A lead-on-chip package manufacturing method includes an insulating liquid adhesive depositing step on lead attaching regions formed on an active surface of a semiconductor on a wafer. The adhesive deposition may be accomplished by a screen printing method in which the adhesive is forced through hole patterns of a metal screen, or by a dispensing method in which a liquid adhesive is dispensed from needles of a dispensing head that is movable over the wafer surface and is aligned with the wafer. The dispensing technique may be applied to a plurality of chips in step-by-step fashion, or in a simultaneous manner by using a multi-needled dispensing head.

Abstract: Disclosed is a semiconductor package and method in which a semiconductor chip is mounted within the opening of a lead frame by bonding wires extending between the active front side of the chip and bonding pads of the lead frame, and the lead frame/chip assembly is encased within a plastic molded body, with the inactive back side of the chip exposed and facing outside the package.

Abstract: A method of encapsulating a semiconductor device. The encapsulation method includes a semiconductor chip package assembly having a spacer layer between a top surface of a sheet-like substrate and a contact bearing surface of a semiconductor chip, wherein the substrate has conductive leads thereon, the leads being electrically connected to terminals on a first end and bonded to respective chip contacts on a second end. Typically, the spacer layer is comprised of a compliant or elastomeric material. A protective layer is attached on a bottom surface of the substrate so as to cover the terminals on the substrate. A flowable, curable encapsulant material is deposited around a periphery of the semiconductor chip after the attachment of the protective layer so as to encapsulate the leads. The encapsulant material is then cured. Typically, this encapsulation method is performed on a plurality of chip assemblies simultaneously.