Abstract: A semiconductor device having a plated heat sink structure is provided, in which an Au layer (5) high in thermal expansion coefficient is formed on the lower surface of a GaAs substrate (1) having a source electrode (2), a gate electrode (3) and a drain electrode (4) of a field effect transistor on the upper surface, and, a W layer (6) low in thermal expansion coefficient is formed on the lower surface of the Au layer (5). Warping of the device after mounted on a package is reduced on the ground of such a plated heat sink structure.

Abstract: Methods of producing a chip scale package that enables any chip with peripheral bond pads to be converted to an area array chip scale package suitable for chip on board assembly. The present invention produces the equivalent of a flip chip die when a chip supplier does not provide one. Processing is performed that provides thin film metal interconnections between the chip bond pads and area array bond pads on the bottom of the package. High reliability thin film metal interconnections are thus provided that connect the bond pads of the chip to the area array bond pads to permit external connection to the chip.

Abstract: A method of fabricating a monolithic device, preferably a micromechanical device, from a wafer (20) by carefully selecting the composition of two or more layers of photoresist (52,54). The present invention comprises choosing compatible photoresist layers to avoid generating defects in the layers of photoresist which could allow a wet chemical HF acid etch process to damage an underlying micromechanical device. The present invention allows a very strong solution of hydrofluoric acid to be utilized to remove particles and debris after a partial-saw process, and to remove a damaged portion of an underlying CMOS layer (22) at a region (68) proximate a kerf (62). Using an HF solution having a concentration of about 6% is desired. The present invention substantially improves the yield of micromechanical devices.

Abstract: An apparatus and a method for increasing integrated circuit density comprising semiconductor wafers, wafer portions or dice ("semiconductor elements") having conductive traces on the back side thereof. These semiconductor elements are stacked such that the traces on the back side of an upper semiconductor become part of the interconnect traces of the semiconductor stacked below. The traces lead to one or more edges of the semiconductor element such that the traces can make electrical contact with an external substrate, leadframe, or wiring arrangement.

Abstract: A method for improving adhesion from a leadframe to a metallic wire is disclosed including using a laser beam to remove selected areas of an package adhesion enhancing layer to expose a layer on the leadframe which has a higher adhesion to metallic wires. The package adhesion enhancing layer is from the group consisting essentially of aluminum oxide, anti-tarnish finishes, and dielectrics.The exposed layer on the leadframe is selected from the group consisting essentially of silver, nickel, palladium.

Abstract: It is intended to provide method for bonding a bump formed on an electronic component to a circuit pattern on a substrate, the method being capable of preventing defective connection due to breakage of the conductive adhesives. The method interposes the conductive adhesives between the bump and the circuit pattern, injects the insulating adhesives between the electronic component and the substrate while the temperature is raised to a temperature for curing the conductive adhesives, and lowered to the room temperature, and cures the insulating adhesives, whereby the electronic component is firmly attached to the substrate still at a high temperature and the substrate subsequently cooled to the room temperature cannot be substantially deformed.

Abstract: A method and apparatus for dissipating heat from a semiconductor device. A heat sink embodying the method includes an exterior surface contoured to better facilitate heat dissipation and/or direct a flow of air or fluid over the heat sink. In one embodiment, the heat sink includes a heat sink layer formed from a powdered metal. In another embodiment, the heat sink layer is contoured with a selected combination of bumps, indentations and holes. In yet another embodiment, the heat sink includes a stack of such heat sink layers which are mechanically interfitted and thermally coupled.

Abstract: A semiconductor pressure detecting device in which a pressure sensing element (2) made of semiconductor having a diaphragm portion (9), a pedestal (8) for supporting the pressure sensing element (2) and wires (5) connected to the pressure sensing element (2) are molded by a molding resin (6) not so as to mold the diaphragm portion (9), characterized in that a silicon resin layer (4) is adhered on an outer surface of the diaphragm portion (9).

Abstract: The main surface of a first semiconductor chip having a first functional element is formed with first testing electrodes for testing the electrical characteristics of the first functional element and first connecting electrodes electrically connected to the first functional element. The main surface of a second semiconductor chip having a second functional element is formed with second testing electrodes for testing the electrical characteristics of the second functional element and second connecting electrodes electrically connected to the second functional element. The first semiconductor chip and the second semiconductor chip are integrated by using an insulating resin, with first bumps formed on the first connecting electrodes being bonded to third bumps formed on the second connecting electrodes.

Abstract: A semiconductor assembly comprising a semiconductor die with bond pads, a plurality of leads which extend across the semiconductor die and terminate over their respective bond pads, and an alpha barrier preferably positioned between the leads and the semiconductor die. Electrical connection is made between the leads and their respective bond pads by a strip of anisotropically conductive elastomeric material, preferably a multi-layer laminate consisting of alternating parallel sheets of a conductive foil and an insulating elastomer wherein the laminate layers are oriented perpendicular to both the bond pad and the lead, positioned between the leads and the bond pads. A burn-in die according to the present invention is also disclosed.

Abstract: A method for producing a glue layer for an integrated circuit which uses tungsten plugs in accordance with the present invention includes: (A) providing a substrate which has a surface, a center, an edge, and a direction normal to the surface; and (B) sputter depositing a glue layer over the surface of the substrate such that an edge thickness of the glue layer measured in the direction normal to the surface at the edge of the substrate is at least 105% of a center thickness of the glue layer measured in the direction normal to the surface at the center of the substrate.

Abstract: A semiconductor package is produced by the following steps. A plurality of circuit boards are prepared, each board having an opening for forming a cavity and a surface providing with a circuit pattern having bonding sections at a peripheral area of the opening. The bonding sections of the respective circuit boards are covered with protective films. A laminated body is formed by laminating the plurality of circuit boards by means of adhesive sheets arranged between the respective circuit boards. Upper and lower substrates are also laminated on upper and lower surfaces of the plurality of circuit boards, respectively, by means of adhesive sheets to close the cavity. The protective films are subsequently removed from the bonding sections of the respective circuit boards of the laminated body.

Abstract: A method for producing a semiconductor device includes: a) an attaching process in which a flat-plate member is positioned on a flat-shape lead frame provided with a plurality of leads and a plurality of support bars so that the flat-plate member contacts at least the plurality of leads, and the flat-plate member is attached to plurality of support bars; b) an element mounting process in which a semiconductor element is mounted on the flat-plate member attached to the plurality of support bars of the flat-shape lead frame; c) a wire-bonding process in which a wire is provided between each of the plurality of leads and the semiconductor element; and d) a separating process, performed after the completion of the wire-bonding process, in which the plurality of support bars are deformed so as to separate the flat-plate member and the plurality of leads and electrically disconnect or separate the flat-plate member from the plurality of leads.

Abstract: A method of assembling flip chips in a package. Solder bumps are attached to a first flip chip and to a second flip chip. A package substrate having first and second opposing sides is provided, and the first flip chip is electrically connected to the first side of the package substrate using the solder bumps attached to the first flip chip. The second flip chip is also electrically connected to the second side of the package substrate using the solder bumps attached to the second flip chip. The position of the second flip chip is substantially opposed to and aligned with the position of the first flip chip. The first and second flip chips are under filled with a heat conductive epoxy. The first flip chip is encapsulated against the first side of the package substrate, and the second flip chip is encapsulated against the second side of the package substrate. Solder balls are attached to the first side of the package insert.

Abstract: A method of producing electronic device packages is provided, consisting of the steps of shaping a package preform and heating the package preform in a nitrogen-containing atmoshpere to nitride the package preform. The shaped package preform may consist of package base, sidewall, conductor, resistor, or capacitor components. The package base and sidewall components may be formed of silicon powder. The method also accommodates the step of inserting a semiconducting material into the package preform and heating the semiconducting material component along with the package preform. The inserted semiconducting material component may be processed to define active electronic device areas on the component either before or after the step of heating the shaped package preform and inserted semiconducting material component.

Abstract: A quad flat pack arrangement which provides for an electrically enhanced integrated-circuit package structure is disclosed. An integrated-circuit die is centrally attached to the top surface of a thermally-conductive, and electrically conductive or insulated substrate. A lead frame having a plurality of inwardly-extending bonding fingers has the bottom sides thereof attached to the top surface of the substrate by a non-conductive adhesive so that an open portion thereof overlies the integrated-circuit die. The plurality of bonding fingers are disposed so as to peripherally surround the integrated-circuit die. A double-sided printed circuit board having first and second conductive layers disposed on its opposite sides is disposed over and bonded to the lead frame. Bonding wires are used to interconnect bonding pads on the integrated-circuit die to the first and second conductive layers. A plastic material is molded around the substrate, die, lead frame, printed circuit board and conductive layers.

Abstract: A microelectronic device is hermetically sealed at the wafer level. A substrate is provided having associated electronics and at least one metal bonding pad. A dielectric layer, such as pyrex glass film, is sputter deposited atop the substrate to form a glass/metal seal. A glass film is thereafter planarized, preferably by chemical-mechanical polishing, to remove surface variations. A cover wafer is thereafter anodically bonded to the dielectric layer/glass film so as to define a sealed cavity for housing and protecting the substrate electronics. The resultant microelectronic device is packaged in its own hermetically sealed container at the wafer level.

Abstract: A plurality of separate semiconductor chips, each having a contact-bearing surface and contacts on such surface, are disposed in an array so that the contact-bearing surfaces face and define a first surface of the array. A flexible, dielectric sheet with terminals thereon overlies the first or contact bearing surface of the semiconductor chips. Elongated leads are disposed between the dielectric element and the semiconductor chips. Each lead has a first end connected to a terminal on the dielectric element, and a second end connected to a contact on a semiconductor chip in the array. All of the leads are formed simultaneously by moving the dielectric element and the array relative to one another to simultaneously displace all of the first ends of the leads relative to all of the second ends. The dielectric element is subdivided after the forming step so as to leave one region of the dielectric element connected to each chip and thereby form individual units each including one chip, or a small number of chips.

Abstract: In a method for manufacturing an electronic apparatus, an electronic component is mounted on an organic substrate within its cavity. The electronic component is sealed by a concave molded resin enveloper filled into the cavity.

Abstract: An interconnection between bonding pads on an integrated circuit chip and corresponding bonding contacts on a substrate are formed. To form the interconnection, a metallization is formed on each of the substrate bonding contacts. Metal ball bond bumps are formed on selective ones of the bonding pads and then coined. The substrate and integrated circuit chip are heated. The coined ball bond bumps are then placed into contact with the corresponding metallizations, pressure and ultrasonic energy are applied, and a metal-to-metal bond is formed between each coined ball bond bump and the corresponding metallization.