Abstract: A system for assigning a network address to a wireless device includes a network server, a virtual device manager, and an address resolution (AR) module. In one embodiment, the system is operable to push information from an information source within a computer network to the wireless device. In this embodiment, the network server is coupled to the computer network, and is operable to receive a network identification for the wireless device from the information source and return a network address associated with the wireless device to the information source. The virtual device manager is also coupled to the computer network, and may be accessed on the computer network using any of a plurality of network addresses, including the network address associated with the wireless device. The AR module is coupled to the virtual device manager, and is operable to receive the network address associated with the wireless device and determine an identification of the wireless device within a wireless network.

Abstract: An error feedback circuit includes a first summer receiving an analog input signal and a feedback signal and outputting a summed signal. A quantizer receives the summed signal and outputs a quantized output signal. A limiter receives the summed signal and outputs a limited summed signal. The limiter limits the limited summed signal to ?* (maximum value of input signal), ?>1. A second summer receives the limited summed signal and the output signal and outputs an error signal. A filter receives the error signal and outputting the feedback signal. Typically, 1.0<?<2.0, more preferably 1.4<?<1.6. The filter has a transfer function of H1(z)=2z?1?z?2.

Abstract: A method for localizing a mobile station, which in one embodiment is characterized by logging one or more wireless channels which belong to one or more network providers other than the mobile station's home network provider and which substantially currently provide communication with one or more discernable base stations; and establishing a geographic position of the mobile station by use of the one or more wireless channels which belong to the one or more network providers other than the mobile station's home network provider. In one or more various embodiments, related systems include but are not limited to circuitry and/or programming for effecting the foregoing-referenced method embodiment, the circuitry and/or programming can be virtually any combination of hardware, software, and/or firmware configured to effect to foregoing-referenced method embodiment depending upon the design choices of the system designer.

Abstract: An acquisition and averaging circuit is provided in which, during a sampling phase capacitors in sample blocks 4 and 6 are sequentially connected to the input signal to sample it and are then isolated so as to hold the sample. The capacitors are then connected to a combining/averaging arrangement such that an average of the sample values is formed.

Abstract: A current sensing analog to digital converter (CS-ADC) is disclosed. The current sensing analog to digital converter comprises a modulator adapted to sense a change in current and generate an oversampled signal. The converter further includes a decimation filter system coupled to modulator for removing out of band noise from the signal and reduce the data rate to achieve a high resolution signal. A current sensing analog to digital converter (CS-ADC) is disclosed that samples the charge or discharge current flowing through an external sense resistor RSENSE. The sample from the RSENSE is processed by a delta-sigma modulator which generates an over sampled noise shaped signal. From this signal a decimation filter system removes the out-of band noise and reduces the data rate to achieve a high-resolution signal. The CS-ADC also provides regular current detection. The regular current detection compares the data from conversion against charge/discharge threshold levels specified by the user.

Abstract: Techniques are disclosed that reduce the computational complexity of PPM-based data compression through use of certain simplifying assumptions that permit faster search for a close-to-optimal PPM model than conventional techniques. The disclosed techniques permit the cost of the computationally-expensive model building task to be amortized over many compression/decompression cycles by maintaining a PersistentModel class, accessible to both the coder and decoder side of the system. This allows the computationally-expensive model building task to be performed only occasionally, as opposed to each time a message is coded. Furthermore, the model-building task is preferably scheduled to run at non-busy times, such that it minimizes user-perceptible service disruptions.

Abstract: A variable length coding apparatus and a variable length coding method including a prepacking unit which processes two data items, each of which is formed with a code value and a code length and is received from a variable length code generator at each clock cycle, into one data item and outputs the processed data item to perform bitstream packing. With this structure, a variable length coding apparatus operating at a high speed without idling can be implemented.

Abstract: A data compression architecture includes a shift register with multiple shift register elements. A data input receives input data characters, and applies each received input data character to the shift register, such that the received input data character is stored in each shift register element of said shift register in turn. Logic circuitry is associated with each shift register element of the shift register, for detecting a match when the comparison circuitry determines that a sequence of two or more received input data characters is equal to a sequence stored in the shift register. A flush input receives a data flush input signal, and applies a received data flush input signal to the logic circuitry associated with each shift register element of the shift register, such that no match is detected by said logic circuitry when the data flush input signal is received.

Abstract: The present invention is related to a method for estimating a movement speed of a mobile unit in a mobile radio communication system. First, a signal from the mobile unit is received. Then, a first signal is generated by using a first filter having a first cut-off frequency to filter the signal. A first speed is obtained based on the first signal. A second signal is further generated by using a second filter having a second cut-off frequency to filter the signal. A second signal is obtained based on the second signal. Then the movement speed of the mobile unit is determined according to the first speed and the second speed.

Abstract: An active hybrid circuit for a full duplex channel generates a duplicated voltage at the current output stage to reduce the energy of the transmitter transmitted to the receiver. The active hybrid circuit cancels the energy of the transmitter transmitted to the receiver when it is operated in a full duplex channel with high-speed transmission. The active hybrid circuit for full a duplex channel comprises a transmit digital-to-analog converter for generating an analog transmit signal, a receive analog-to-digital converter for receiving an analog receive signal, a duplicated voltage digital-to-analog converter for generating a corresponding duplicated voltage according to the analog transmit signal of the transmit digital-to-analog converter, and a plurality of signal combiners for subtracting the duplicated voltage from the analog transmit signal to cancel the influence of analog transmit signal to the analog receive signal.

Abstract: A time-analog-to-digital converter (TAD) utilizes a time-to-digital approach for analog-to-digital conversion. The TAD includes two voltage-to-delay converters (VDCs), e.g., CMOS inverter chains, in order to increase the dynamic range of the TAD. Each VDC can handle a different range of input voltages. Comparators compare the input signal voltage to reference voltages corresponding to the different ranges of input voltage and a selector selects one of the VDC line outputs based on the range in which the input signal lies. A filter estimates the input signal voltage from a delay signal from the selected output.

Abstract: A five-level feed-back digital-to-analog converter (DAC) in a switched capacitor sigma-delta analog-to-digital converter has an improved switching sequence that boosts from two to five the number of quantization levels of the feed-back DAC. Switching sequences are used to obtain five equally distributed charge levels C*VREF, C*VREF/2, 0, ?C*VREF/2 and ?C*VREF. When summed with an input voltage, VIN, the five-level feed-back DAC produces five equally distributed output voltages of A*VIN+VREF, A*VIN+VREF/2, A*VIN+0, A*VIN?VREF/2 and A*VIN?VREF, where A is gain, VIN is the input voltage, and VREF is the reference voltage.

Abstract: Method and system for planning and/or evaluation of cell capacity in (CDMA) radio networks comprising at least one base station that defines at least one cell. Both uplink cell capacity estimations and downlink cell capacity estimations can be made by adding amounts of traffic to the cell until a limiting capacity representative value has been reached.

Abstract: An AD converter includes therein a plurality of amplifier circuits such as first to fourth amplifier circuits. Among the plurality of amplifier circuits an amplifier circuit that requires higher accuracy is placed nearer to a power source. An amplifier circuit that receives the first input of an input analog signal is placed nearest to the power source. That is, the first amplifier circuit in the embodiment is disposed closest to the power source. The amplifier circuit that receives the first input of an input analog signal is disposed closest to the power source compared to the other amplifier circuits. The first amplifier circuit, the second amplifier circuit, the third amplifier circuit and the fourth amplifier circuit in the embodiment are placed in this order of how close to the power source.

Abstract: The need for reducing the time required for call setup in a wireless communication system (100) is addressed herein. A base station (BS 104) sends a channel assignment message to a mobile station (MS 102) and performs traffic channel initialization procedures with the MS. After completing the traffic channel initialization procedures, the BS sends a base station acknowledgment message to the MS and proceeds to transmit signaling to the MS without waiting to receive an MS acknowledgment in response to the base station acknowledgment message. Thus, the time normally taken to receive the MS acknowledgment is saved and call setup time reduced.

Abstract: A location system for use in a mobile communication network includes base stations which transmit known signals at predetermined times for use in deriving location data; a first transmitting and receiving units; a unit for determining times of arrival of the known signals from each base station at each of the first transmitting and receiving units; a unit for determining times of arrival of the known signals from each base station at a second transmitting and receiving unit at an unknown location; a comparing unit for comparing timing differences between the known signals received at the first transmitting and receiving units and the second transmitting and receiving unit; and location determining unit for determining the location of the second unit. Each of the first transmitting and receiving units includes a unit for deriving its location from a further set of received signals such as GPS signals.

Abstract: To provide a service with fairness by providing QoS of approximately an equal degree among users of the same service class to keep fairness of the service as well as by maintaining a transmission rate at a predetermined ratio among users of different service classes to relatively keep QoS among service classes.

Abstract: A low noise amplifier (500) includes a first transconductance device (326) having a control electrode for receiving a first input signal, and a first current electrode; a first load device (322) having a first terminal coupled to a first power supply voltage terminal and a second terminal coupled to the first current electrode of the first transconductance device (326) and forming a first output voltage signal; a second transconductance device (336) having a control electrode for receiving a second input signal, and a second current electrode; a second load device (332) having a first terminal coupled to the first power supply voltage terminal and a second terminal coupled to the first current electrode of the second transconductance device (336) and forming a second output voltage signal; and an attenuation device (340) coupled between the first current electrodes of the first (326) and second (336) transconductance devices and having a control input terminal for receiving a control voltage thereon.

Abstract: Described is a system for trimming the value of an electronic component. The system comprises: at least one trimming component, each trimming component having an associated switch for selectively connecting that trimming component to the electronic component in response to a corresponding bit in a control vector. A comparator is included for generating an output bit having a first value if a net value of the electronic component and any connected trimming components differs from a desired value. A controller connected to the switches and the comparator generates the control vector in dependence on the output of comparator, the controller comprising a shift register for sequentially receiving successive output bits from the comparator; wherein the control vector comprises the contents of the shift register and wherein a bit of said first value in control vector effects switching of the corresponding switch.

Abstract: Look-ahead delta sigma modulators of the signal processing systems described herein can anticipate quantizer overload. By anticipating quantizer overload, the look-ahead delta sigma modulators can select an output value y(n) that may have a lower SNR but will prevent quantizer overload in the future. A quantizer overload protection process determines the amount of look-ahead depth to drive state variables of a loop filter of the look-ahead delta sigma modulator to values that would prevent future quantizer overload. By substituting a quantizer of the look-ahead delta sigma modulator with a gain and determining a closed loop impulse response of a look-ahead delta-sigma modulator, the discrete time to achieve an absolute value maximum closed loop response magnitude of the look-ahead delta-sigma modulator has been determined to be directly related to the look-ahead depth that will prevent future quantizer overload.