Abstract: An apparatus includes a processor and a memory configured to store design data used for disposition and wiring of a logic circuit on a programmable logic device, and store a table indicating a relationship between a power supply voltage value and a delay amount for each type of element in the logic circuit, the relationship having a nature to set the delay amount so as to increase in value as the power supply voltage value is smaller. The processor determines, as an optimum voltage value, a power supply voltage value at which the delay margin of a critical path indicates a desired value that is in the positive and is a minimum value. The processor outputs configuration information including the optimum voltage value and the design data so as to form the logic circuit on the programmable logic device supplied with a voltage determined by the optimum voltage value.

Abstract: Voltage regulation of processor sub-domains supplied by a same voltage domain power supply rail. Voltage to certain logic units within the voltage domain may be reduced relative to other logic units of the voltage domain, reducing idle time at high power. In an embodiment, a first voltage-regulated sub-domain includes at least one execution unit (EU) while a second voltage-regulated sub-domain includes at least one texture sampler to provide flexibility in setting the graphics core power-performance point beyond modulating active EU count through power domain (gating) control. In embodiments, a sub-domain voltage is regulated by an on-chip DLDO for fast voltage switching. Clock frequency and sub-domain voltage may be switched faster than the voltage of the voltage domain supply rail, permitting a more finely grained power management that can be responsive to EU workload demand.

Abstract: Device drivers are provided from virtual media. System resources trap input/output data associated with the device drivers. Memory is allocated for the virtual media and populated with the device drivers using the input/output data. As an operating system installs, the virtual media is readable and is accessed for the device drivers.

Abstract: In a system using a device not adapted to a single wire bus, a semiconductor device includes an external terminal to be coupled to a power source terminal of an external device, a port that supplies a power source voltage for the external device to the external terminal, a power manager that controls an output of the port, and a CPU that controls an operation of the power manager.

Abstract: A method may include associating, with a timer-B, a second application in a terminal device; setting the terminal device in a standby mode; and executing the second application when a processor in the terminal device wakes up after the timer-B measures a second amount of elapsed time. The timer-B may not initiate wake-up of the processor. The method may further include determining whether the second application is associated with the timer-B or a timer-A when the terminal device receives a command of setting the terminal device in the standby mode; and when the second application is determined as being associated with the timer-A, unassociating the second application with the timer-A. The timer-A may initiate wake-up of the processor when the timer-A measures another second amount of elapsed time while the terminal device is the standby mode. A timer associated with a first application may initiate wakeup of the processor.

Abstract: A power supply system for a motherboard includes a switching power source, a control circuit, and a switch circuit. The control circuit includes a photocoupler and a comparator. The photocoupler is electrically connected to the switching power source and the comparator. The switch circuit is electrically connected to the comparator and a motherboard. The switch circuit is turned off when the motherboard is in a normal state and turned on when the motherboard is in a standby state. The switching power source outputs a voltage through the control circuit when the switch circuit is turned off. When the switch circuit is turned on, the comparator outputs a first state signal to the photocoupler. The photocoupler thus outputs a first driving signal to the switching power source. The first driving signal causes the switching power source to reduce the voltage.

Abstract: A microcontroller that can be configured to selectively operate in a synchronous mode or an asynchronous mode, and a method of selectively switching the operating mode is described. The microcontroller can include a processor and a system controller. The processor can be configured to operate synchronously in a synchronous operating mode and asynchronously in an asynchronous operating mode. The processor can also be configured to generate a processor idle status signal indicative of the processor operating in a reduced power mode, and generate a programming signal. The system controller can be configured to generate an asynchronous mode signal based on the programming signal and the processor idle status signal, and provide the asynchronous mode signal to the processor to control the processor to selectively operate in the synchronous operating mode and in the asynchronous operating mode.

Abstract: A method of synchronizing a feature between a first vaping system comprising a first electronic vapor provision system and a second vaping system including a second electronic vapor provision system, wherein the first and second vaping systems are members of a synchronization group, includes associating the first vaping system with a group identification (ID) associated with the synchronization group; detecting a signal from the second vaping system, the signal including data indicating that the second vaping system is a member of the group; and modifying a setting associated with an illuminated portion of the first electronic vapor provision system to a setting common to members of the group.

Abstract: A system and method for message analysis, including: receiving, by a control service, a first modification request to modify a file system of a computing device, wherein the computing device is operating in a read-only state; identifying, by the control service, a request parameter associated with the first modification request; determining, by the control service, that the request parameter satisfies a permission criteria to perform the first modification request; provisioning, by the control service, the computing device to operate in a read/write state in response to determining that the permission criteria has been satisfied, wherein the first modification request is executed to modify the file system while the computing device is operating in the read/write state; and, upon a determination that the first modification request has successfully completed, provisioning, by the control service, the computing device to operate in the read-only state.

Abstract: Described is a multi-purpose power controller and application specific standard product (ASSP) with improved block unification, reduced size and power, boot strapping, and power management. A multi-purpose field programmable non-volatile system power controller and ASSP initializing block may be embedded in a processor, such as a central processing unit (CPU), graphics processing unit (GPU), accelerated processing unit (APU), or other chipset. This controller and initializing block may be a configurable, while maintaining specialization, hardware block. This block may be implemented as a complex programmable logic device or as a simple cascaded programmable logic array block, such as being the equivalent of a few hundred logic gates, for example. Described also is a method of performing power sequencing and boot strapping for internal and external blocks on a chipset. The method includes powering a system power controller and initializing block and saving a power-up sequencing in a nonvolatile wake-up table.

Abstract: A time of day (TOD) synchronization mechanism in a first processor transmits a latency measure message simultaneously on two links to a second processor. In response, the receiver in the second processor detects latency differential between the two links, detects the delay in the second processor, and sends the latency differential and delay to the first processor on one of the two links. The first processor stores TOD delay values in the two links that account for the latency differential between the two links. When a TOD message needs to be sent, a link loads a counter with its stored TOD delay value, then decrements the counter until the TOD message is ready to be sent. The resulting counter value is the receiver delay value, which is transmitted to the receiver as data in the TOD message, thereby reducing TOD jitter between the two links.

Abstract: An integrated circuit is disclosed for power multiplexing with an active load. In an example aspect, the integrated circuit includes a first power rail, a second power rail, a load power rail, multiple power-multiplexer tiles, and power-multiplexer control circuitry. The first power rail is at a first voltage, and the second power rail is at a second voltage. The multiple power-multiplexer tiles are coupled in series in a chained arrangement and jointly perform a power-multiplexing operation responsive to a power-rail switching signal. Each power-multiplexer tile switches between coupling the load power rail to the first power rail and the second power rail. The power-multiplexer control circuitry is coupled to the first and second power rails and includes a comparator to produce a relative voltage signal based on the first and second voltages. The power-multiplexer control circuitry generates the power-rail switching signal based on the relative voltage signal.

Abstract: An embedded system has a data processing apparatus that executes program code and a sequencing controller for switching components of the embedded system on and off, the data processing apparatus and the sequencing controller connected to one another via an individual control signal line, and the sequencing controller arranged to either switch off or restart the embedded system on the basis of a temporal profile of a control signal received via the control signal line.

Abstract: An apparatus, method and system is described herein for efficiently balancing performance and power between processing elements based on measured workloads. If a workload of a processing element indicates that it is a bottleneck, then its performance may be increased. However, if a platform or integrated circuit including the processing element is already operating at a power or thermal limit, the increase in performance is counterbalanced by a reduction or cap in another processing elements performance to maintain compliance with the power or thermal limit. As a result, bottlenecks are identified and alleviated by balancing power allocation, even when multiple processing elements are operating at a power or thermal limit.

Abstract: The present invention ensures more secure connections between devices that comply with a USB power delivery standard. In an embodiment, a power feeding system 1 selects one of a plurality of power supply voltages and performs a power feeding operation via a USB interface, and the power feeding system includes: a USB cable 30 including a security controller 38 that holds security information, and a host 10 that is connected to the USB cable 30, includes an authenticator controller 14, the authenticator controller 14 authenticating the USB cable 30 using the security information received from the USB cable 30, receives a voltage selection signal that selects one of the plurality of power supply voltages, and performs a power feeding operation based on the voltage selection signal. The host 10 carries out the power feeding operation based on the voltage selection signal when the authentication has been successfully performed.

Abstract: An apparatus may include detection circuitry configured to detect a presence of a host clock signal on a host clock line, and detect a level of a host supply voltage upon detection of the host clock signal. The detection circuitry may configure a core regulator in a regulation mode or in a bypass mode based on the detected level of the host supply voltage. Additionally, components of analog circuitry of a non-volatile memory system may be partitioned into different supply voltage domains, with those components active during a sleep state receiving one supply voltage and those components inactive during the sleep state receiving a different supply voltage.

Abstract: A method and an information handling system (IHS) provides a virtual alternating current (vAC) reset of the IHS. A vAC reset module (vACRM), in response to receiving a request for the vAC reset, sets a bit within an auxiliary (AUX) based register to invoke the vAC reset when a system restart command is issued. The vACRM changes/configures a vAC recovery policy to enable main rail power to be turned on and a system start-up procedure to be initiated when a restored vAC is detected. The vACRM uses a system restart command to shutdown the main rail power and to remove power from system components powered by the main rail. The vACRM switches off AUX power to AUX powered components, based on the previously set bit, and reapplies the AUX power, following a preset interval. The vACRM turns on main rail power and initiates a system start-up procedure, according to the vAC recovery policy.

Abstract: A method, information handling system (IHS) and sub-system for enabling booting of the IHS using different operating system configurations. The method includes retrieving, via a processor, a unified extensible firmware interface (UEFI) image from a storage device and initializing at least one UEFI runtime service. The processor determines if a memory map corresponding to the UEFI runtime service defines multiple memory descriptors. In response to determining that the memory map defines multiple memory descriptors, a common memory descriptor is identified. The UEFI runtime service and the corresponding memory map are aligned to the common memory descriptor. The aligned UEFI runtime service and the corresponding memory map are copied to a system memory of the IHS. The operating system is booted, wherein the aligned UEFI runtime service and the corresponding memory map are compatible with operating systems that support single runtime memory descriptors.

Abstract: Adjusting a computing environment for processing a data stream involves identifying one or more dummy tuples in the data stream processed by the computing environment. Propagation of the identified dummy tuples to be processed through a plurality of operators in the computing environment is controlled in order to control adjustment of the computing environment. The computing environment is adjusted based on the processing of the propagated dummy tuples.

Abstract: An input part sets either a charge time zone or a discharge time zone. A first firmware storage part stores first firmware defining all operation contents of a power supply device. An acquiring part acquires second firmware that is firmware for update, and a second firmware storage part stores the second firmware. A controller refers to the charge time zone, the discharge time zone and the like received from the input part to extract a first time zone in which neither the charge time zone nor the discharge time zone is set. The controller preferentially sets timing for updating firmware in the first time zone.