Abstract: An input part sets either a charge time zone or a discharge time zone. A first firmware storage part stores first firmware defining all operation contents of a power supply device. An acquiring part acquires second firmware that is firmware for update, and a second firmware storage part stores the second firmware. A controller refers to the charge time zone, the discharge time zone and the like received from the input part to extract a first time zone in which neither the charge time zone nor the discharge time zone is set. The controller preferentially sets timing for updating firmware in the first time zone.

Abstract: In an embodiment, an integrated circuit may include one or more processors. Each processor may include multiple processor cores, and each core has a different design/implementation and performance level. For example, a core may be implemented for high performance, but may have higher minimum voltage at which it operates correctly. Another core may be implemented at a lower maximum performance, but may be optimized for efficiency and may operate correctly at a lower minimum voltage. The processor may support multiple processor states (PStates). Each PState may specify an operating point and may be mapped to one of the processor cores. During operation, one of the cores is active: the core to which the current PState is mapped. If a new PState is selected and is mapped to a different core, the processor may automatically context switch the processor state to the newly-selected core and may begin execution on that core.

Abstract: Methods and systems are disclosed for booting an integrated circuit (IC). In an example implementation, boot read only memory (ROM) code is loaded for execution by a processor circuit of the IC. Via execution of the boot ROM code on the processor circuit, a first boot image is retrieved. A memory address is communicated from a host device to the processor circuit of the IC via an external data bus coupled to a bus interface circuit in the IC. The bus interface circuit is configured by execution of the first boot image to map a first block of addresses on the internal data bus to a second block of addresses on the host device starting at the memory address. When bus mastering is enabled, the processor retrieves a second boot image from the host device by issuing read requests to the first block of addresses.

Abstract: A semiconductor device having an active mode and a standby mode as operation modes, includes a first power supply line supplied with a first internal power supply voltage from a first external power supply and an internal power supply circuit generating a second internal power supply voltage based on an external power supply voltage from a second external power supply circuit. A second power supply line supplied with said second internal power supply voltage from said internal power supply circuit.

Abstract: Disclosed are various embodiments for a timeout management application. Latency data for executing services is obtained. The used service capacity is calculated. If the service capacity is outside of a predefined range, the timeout of a selected service is reconfigured.

Abstract: In one embodiment, the present invention includes a method for providing power state change information from a plurality of cores of a processor to a predictor at a periodic interval and generating a prediction to indicate a predicted operation level of the cores during a next operating period. Other embodiments are described and claimed.

Abstract: Disclosed herein are intelligent electronic devices configured for monitoring an electric power delivery system and for determining a plurality of configuration settings based on measurements from the electric power delivery system. An IED may identify a configuration event, obtain a plurality of electrical parameters associated with the configuration event, determine a plurality of configuration parameters from the electrical parameters, determine a plurality of configuration settings based on the configuration parameters, and apply the settings to the IED. The IED may also be configured to initiate the configuration event by opening a single pole of a multi-phase power line.

Abstract: Provided is a process of managing rack-mounted computing devices in a data center with a distributed peer-to-peer management system, the process including: determining roles of data-center management computing devices in a distributed peer-to-peer data-center management system; receiving, via an out-of-band network, a data-center management command at a given data-center management computing device; distributing, based on at least some of the roles, via the out-of-band network, the data-center management command.

Abstract: A device for processing data includes a processing unit configured to predict an execution time of a compute kernel on a secondary processing unit and, based on the predicted execution time, make a power management decision for the secondary processing unit.

Abstract: Embodiments of the present disclosure disclose a method for starting an application program, a terminal and a non-transitory computer readable storage medium, relating to the field of communications, for providing a method capable of quickly starting an application program without starting each functional module of the terminal. In the embodiments of the present disclosure, after a minimum system of the terminal is started, a preset quick start interface is loaded through a display module of the minimum system, wherein the quick start interface at least comprises a plurality of virtual hotkeys for identifying application programs to be started; according to an operation on a virtual hotkey corresponding to starting of an application program, a virtual system executes an operation of starting the application program, wherein the virtual system and a host system of the terminal share physical resources of the terminal.

Abstract: The power consumption of an analog arithmetic circuit is reduced. The analog arithmetic circuit includes a plurality of first circuits. An output terminal of the k-th (k is a natural number) first circuit is connected to an input terminal of the k+1-th first circuit. Each of the first circuits includes a memory circuit which holds an analog signal, a second circuit which performs arithmetic processing using the analog signal, a switch which controls power supply to the second circuit, and a controller. The conduction state of the switch included in the k-th first circuit is controlled by the controller included in the k+1-th first circuit. The arithmetic processing performed by the second circuit included in the k+1-th first circuit is started by the controller included in the k+1-th first circuit.

Abstract: A semiconductor chip device include device state fuses that may be used to configure various device states and corresponding security levels for the semiconductor chip as it transitions from wafer manufacturing to provisioned device. The device states and security levels prevent the semiconductor chip from being accessed and exploited, for example, during manufacturing testing. A secure boot flow process for a semiconductor chip over its lifecycle is also disclosed. The secure boot flow may start at the wafer manufacturing stage and continue on through the insertion of keys and firmware.

Abstract: A first request signal that indicates a request for a time maintained by a clock implemented in first circuitry is sent from second circuitry. The first circuitry utilizes a first clock signal derived from a first oscillator and the second circuitry utilizes a second clock signal derived from a second oscillator. The first circuitry adjusts a first time value from the clock to compensate for a first latency or jitter caused by converting the first request signal to a second request signal synchronized to the first clock. The second circuitry further adjusts the adjusted first time value to generate a second time value that compensates for i) a second latency between sending the first request signal and receiving the adjusted first time value, and ii) a third latency or jitter caused by synchronizing the adjusted first time value to the second clock.

Abstract: In one embodiment, an integrated circuit includes a power management architecture in which one or more pipelines are actively powered and clocked when data is provided for processing, but which are clock gated and in retention when there is no data to be processed. When data is provided to the pipeline, supply voltage may be actively provided to initial stages of the pipeline and the clocks may be ungated when the voltage is stable enough for operation. Subsequent stages of the pipeline may be sequentially provided power and clocks as the data progresses through the pipeline. Initial stages may be clock gated and power may be deactivated when additional data is not provided for processing. Accordingly, when the pipeline is viewed as a whole, power may be seen as rolling forward ahead of the data processing, and power may be inhibited in a similar rolling fashion.

Abstract: A method is described and in one embodiment includes, for each of a plurality of outgoing ports of a first network element: collecting data comprising a number of packets arriving the outgoing port and an amount of power consumed by the outgoing port for a first time interval; calculating a packet per watt (“P/W”) metric for the port for the first time interval, wherein the P/W metric comprises the number of packets coming into the port divided by the amount of power consumed by the port during the first time interval; repeating the collecting and calculating for a number of successive time intervals; calculating a mean P/W metric for a time period comprising the first time interval and the successive time intervals; and calculating a variance for the time period comprising the first time interval and the successive time intervals. The method further includes redirecting traffic received at the network element to the outgoing port having the lowest variance.

Abstract: A microprocessor includes a plurality of processing cores and a configuration register configured to indicate whether each of the plurality of processing cores is enabled or disabled. Each enabled one of the plurality of processing cores is configured to read the configuration register in a first instance to determine which of the plurality of processing cores is enabled or disabled and generate a respective configuration-related value based on the read of the configuration register in the first instance. The configuration register is updated to indicate that a previously enabled one of the plurality of processing cores is disabled. Each enabled one of the plurality of processing cores is configured to read the configuration register in a second instance to determine which of the plurality of processing cores is enabled or disabled and generate the respective configuration-related value based on the read of the configuration register in the second instance.

Abstract: A method includes: determining whether individualized system data are one or more of: installed on, associated with, and up-to-date with respect to a computer system and/or a hardware component of the computer system; and in response to determining the individualized system data are one or more of: not installed on, not associated with, and not up-to-date with respect to the computer system and/or the hardware component, one or more of: installing the individualized system data to one or more of the computer system and the hardware component; associating the individualized system data with one or more of the computer system and the hardware component; and updating out-of-date individualized system data of one or more of the computer system and the hardware component. Corresponding systems and computer program products are also disclosed.

Abstract: In one aspect a disclosed method may include determining, by an information handling system, a future predicted system time that an unattended task is to be executed on the information handling system. The future predicted system time is based at least in part on first usage parameters for a user indicating first periods of usage activity, second periods of inactivity associated with the information handling system recorded during a first duration, and critical system parameters relevant to the present state of the information handling system. The method may also include ensuring that system resources of the information handling system are available for the unattended task to be able to complete. In response to the arrival of the future predicted system time, the unattended task is executed.

Abstract: A method for configuring a communication module of at least one RFID reader that is connected via the communication module to a communication network, wherein the at least one RFID reader is connected to the communication module via a serial interface, wherein configuration information comprising at least communication network address information and device type information is stored in a configuration storage unit of the communication module, where the configuration information stored in the configuration storage unit of the communication module is conveyed via the serial interface to the at least one RFID reader and stored there in a predetermined configuration storage area, and where the configuration information stored in the predetermined configuration storage area of the RFID reader is loaded during a device start of a replacement communication module used instead of the communication module after a successful validity check for configuration of the replacement communication device.

Abstract: Systems and methods are provided that may be implemented to securely load Unified Extensible Firmware Interface (UEFI) images (e.g., UEFI Applications, UEFI Drivers, UEFI firmware volumes, etc.) onto an information handling system from an authenticated (e.g., OEM authenticated) hardware image source device or “IO store” (e.g., such as USB device, network file system device, PCIe device, network storage, shared storage, dynamic RAM disk, etc.) based on a UEFI virtual device path that is mapped to an authenticated hardware device path that is established for the authenticated hardware image source device.