Abstract: A system includes an ARM core processor, a programmable regulator, a compiler, and a control unit, where the compiler uses a performance association outcome to generate a 2-bit regulator control values encoded into each individual instruction. The system can provide associative low power operation where instructions govern the operation of on-chip regulators or clock generator in real time. Based on explicit association between long delay instruction patterns and hardware performance, an instruction based power management scheme with energy models are formulated for deriving the energy efficiency of the associative operation. An integrated voltage regulator or clock generator is dynamically controlled based on instructions existing in the current pipeline stages leading to additional power saving. A compiler optimization strategy can further improve the energy efficiency.

Abstract: Examples of the present disclosure provide an electronic device in a package, the electronic device comprising a first circuit having a temperature sensitive behavior and a second circuit being switchable between a first operating mode and at least one second operating mode. A power consumption of the second circuit in the first operating mode is higher than a power consumption of the second circuit in the second operating mode. The electronic device comprises a controller configured to switch the second circuit into the first operating mode during a first time interval and into the second operating mode during a second time interval. The controller is further configured to cause an additional power consumption in the electronic device during the second time interval to reduce or compensate a difference between an overall power consumption of the electronic device during the first time interval and the second time interval.

Abstract: Disclosed herein are techniques for maintaining a secure execution environment on a server. In one embodiment, the server includes a non-volatile memory storing firmware, a programmable security logic coupled to the non-volatile memory, an adapter device coupled to the programmable security logic, and a processor communicatively coupled to the non-volatile memory via the programmable security logic. The adapter device and/or the programmable security logic can verify the firmware in the non-volatile memory while holding the processor and/or a baseboard management controller (BMC) in power reset, release the processor and the BMC from reset to boot the processor and the BMC after the firmware is verified, and then disable communications between the processor and the BMC and deny at least some requests to write to the non-volatile memory by the processor or the BMC.

Abstract: One embodiment provides a method, including: obtaining, using a processor, a system power consumption metric; determining, using a processor, a change in the system power consumption metric over time; obtaining, using a processor, system change data; associating, using a processor, the change in the system power consumption metric and the system change data; and indicating, using an output device, a system change associated with the change in the system power consumption metric. Other aspects are described and claimed.

Abstract: One embodiment provides a method, including: obtaining, using a processor, a system performance metric; determining, using a processor, a change in the system performance metric over time; obtaining, using a processor, system change data; associating, using a processor, the change in the system performance metric and the system change data; and indicating, using an output device, a system change associated with the change in the system performance metric. Other aspects are described and claimed.

Abstract: In one embodiment, the present invention includes a method for receiving an interrupt from an accelerator, sending a resume signal directly to a small core responsive to the interrupt and providing a subset of an execution state of the large core to the first small core, and determining whether the small core can handle a request associated with the interrupt, and performing an operation corresponding to the request in the small core if the determination is in the affirmative, and otherwise providing the large core execution state and the resume signal to the large core. Other embodiments are described and claimed.

Abstract: A system and method to determine a power-up parameter for a circuit board. The method includes electrically exciting a second-order circuit to generate an underdamped transient response. The method includes receiving, at a comparator coupled to the second-order circuit, the underdamped transient response. The method includes generating, in response to the underdamped transient response received at the comparator, a plurality of edges. The method includes receiving, at a single general purpose input/output pin of the electronic processor, the plurality of edges. The method includes determining a first response parameter based on a plurality of edges. The method includes determining a second response parameter based on the plurality of edges. The method includes determining the power-up parameter based on the first response parameter and the second response parameter.

Abstract: Systems and methods for performing power monitoring calibration to a target performance level are described. In some embodiments, an Information Handling System (IHS) may include a plurality of Central Processing Units (CPUs) and a logic circuit coupled to the plurality of CPUs, the logic circuit configured to: measure an operating performance level for each of the plurality of CPUs under a controlled workload and, in response to a determination that the operating performance level of any given one of the CPUs does not match a target performance level for all of the CPUs, apply an offset to a voltage regulator measurement associated with the given CPU that causes the operating performance level of the given CPU to match the target performance level for all of the CPUs.

Abstract: A microprocessor includes a plurality of processing cores and a configuration register configured to indicate whether each of the plurality of processing cores is enabled or disabled. Each enabled one of the plurality of processing cores is configured to read the configuration register in a first instance to determine which of the plurality of processing cores is enabled or disabled and generate a respective configuration-related value based on the read of the configuration register in the first instance. The configuration register is updated to indicate that a previously enabled one of the plurality of processing cores is disabled. Each enabled one of the plurality of processing cores is configured to read the configuration register in a second instance to determine which of the plurality of processing cores is enabled or disabled and generate the respective configuration-related value based on the read of the configuration register in the second instance.

Abstract: A frequency calibration method applied to a Universal Serial Bus (USB) device includes: coupling the USB device to a USB host, wherein the USB device comprises at least a programmable oscillator; utilizing the USB device to extract a low frequency periodic signal from the USB host; calibrating the programmable oscillator of the USB device according to the low frequency periodic signal, to make the programmable oscillator generate an oscillating signal having a predetermined frequency; and when the USB device receives the low frequency periodic signal from the USB host, controlling the USB device to generate a predetermined signal having a frequency higher than a frequency of the low frequency periodic signal to the USB host, to make the USB host continuously generate the low frequency periodic signal to the USB device.

Abstract: In one example, a computing device including a mass storage medium. The mass storage medium has a pre-installed operating system but no pre-installed partition table. The mass storage medium has pre-installed boot software to generate and store a partition table on the mass storage medium. The partition table is usable by the operating system to access information on the mass storage medium.

Abstract: An arithmetic processing device includes a plurality of arithmetic processing units each including, an internal circuit that, in an instruction processing state in which an instruction is processed, processes the instruction and that, in an instruction processing stopped state in which instruction processing is stopped, transitions to a state of power save operation, and a power control circuit that disables the power save operation; and a monitoring circuit that monitors the instruction processing stopped state of the plurality of arithmetic processing units and counts the number of the arithmetic processing units in the instruction processing stopped state. The power control circuit of each of the plurality of arithmetic processing units disables the power save operation of the arithmetic processing unit in the instruction processing stopped state, in a case where the number of the arithmetic processing units in the instruction processing stopped state exceeds a threshold.

Abstract: Examples herein disclose a command to control a use of a test key for installation of a test basic input output system (BIOS). The examples validate a command and replace at least a portion of a production BIOS with the test BIOS based on an allowance of the test key.

Abstract: In an embodiment, a processor may include a first clock circuit to generate a first clock signal, a plurality of functional blocks, and clock logic. Each functional block may include a sub-clock circuit to generate a second clock signal based on the first clock signal, and a counter to store a count of active consumer of the second clock signal. The clock logic may, in response to a determination that the counter of a first functional block has a value less than one, disable the sub-clock circuit of the first functional block. Other embodiments are described and claimed.

Abstract: Aspects include computing devices, apparatus, and methods implemented by the apparatus for implementing multiple split snoop directories on a computing device having any number of processors, any number of power domains, and any number of processor caches. For example, various aspects may include enabling a first split snoop directory for a first power domain and a second split snoop directory for a second power domain, wherein the first power domain includes a first plurality of processor caches and the second power domain includes at least one processor cache, determining whether all of the first plurality of processor caches are in a low power state, and disabling the first split snoop directory in response to determining that the first plurality of processor caches are in a low power state. Similar operations may be performed for N number of power domains and M number of processor caches.

Abstract: An approach is provided for determining whether to reboot a computing node. Data specifying user behaviors and intra-box and inter-box factors associated with computing nodes are collected and classified in groups. Rules corresponding to the groups are generated. Each rule includes an indicator of whether the corresponding group is associated with permitting or not permitting a reboot. Computing node data is received which specifies intra-box and inter-box factors of the computing node and user operations of the computing node. After determining that the computing node data matches one of the groups, it is determined that a rule corresponding to the group includes an indicator of whether the computing node is permitted to be rebooted. Based on the indicator, the computing node is rebooted or not rebooted.

Abstract: A computer system is securely booted by executing a boot firmware to locate a boot loader and verify the boot loader using a first key that is associated with the boot firmware. Upon verifying the boot loader, computer system executes the boot loader to verify a system software kernel and a secure boot verifier using a second key that is associated with the boot loader. The secure boot verifier is then executed to verify the remaining executable software modules to be loaded during boot using a third key that is associated with the secure boot verifier. During boot, state data files of the computer system are mounted in a namespace that is isolated from the namespaces in which the executable software modules are mounted.

Abstract: A communications system and method provide power-saving while maintaining required protocol timing resolution. In a communication system that requires a high-frequency, high-precision, but high-power, clock source to meet timing requirements, selective disablement and re-enablement of the high-frequency clock provides for both timing precision and power reduction in the system.

Abstract: A computer system is rebooted upon crash without running platform firmware and without retrieving all of the modules included in a boot image from an external source and reloading them into system memory. The reboot process includes the steps of stopping and resetting all of the processing units, except one of the processing units that detected the crash event, selecting the one processing unit to execute a reboot operation, and executing the reboot operation to reboot the computer system.

Abstract: The present invention relates to a method for updating a firmware on a device, from a current version to a new version, said firmware being split into: —a core part, —an extended part comprising a plurality of entry points callable by the core part, said method comprising: —inhibiting the entry points between the core part of the current version, called current core part, and the extended part of the current version, called current extended part; —erasing the current extended part; —downloading the core part of the new version, called new core part; —erasing the current core part; —downloading—the extended part of the new version, called new extended part; —activating the entry points between the new core part and the new extended part.