Abstract: The anti-windup circuit generally has a voltage clamping device in series with a current limiting device operatively connectable to the output current path of a feedback compensator; the feedback compensator being part of a switch-mode power supply (SMPS) having an input voltage source and a load and generating constrained control values required to generate control on-off actions for tight power regulation. The inclusion of the disclosed anti-windup circuit in an SMPS may lead to hardware based overvoltage protection, reduced overall size and faster response to load changes.

Abstract: A front-end module comprises a bias network including a current mirror, a junction temperature sensor, an n-bit analog-to-digital converter, an n-bit current source bank configured to automatically set reference current levels for one or more operating temperature regions, and a power amplifier. The bias network, junction temperature sensor, n-bit analog-to-digital converter, n-bit current source bank, and power amplifier are integrated on a first semiconductor die.

Abstract: A front-end module comprises a low-dropout (LDO) voltage regulator, a reference current generator, and a power amplifier. The LDO voltage regulator, reference current generator, and power amplifier are integrated on a first semiconductor die.

Abstract: Circuits and methods that compensate for the problems created by low-dropout regulator (LDO) leakage current, particularly when stressed. Embodiments include an improved LDO configured to provide a load current, and which includes a leakage current compensation circuit. The leakage current compensation circuit generates a compensating current that offsets the leakage current through the pass device of the LDO during conditions that induce such leakage. More specifically, the leakage current compensation circuit can replicate the leakage current of the pass device of the LDO and feed a compensating current back into the LDO from a current mirror circuit while drawing zero-power during normal use, when leakage current is absent. LDO circuits that include a leakage current compensation circuit are particularly useful as voltage sources for positive or negative charge pumps, but are also quite useful in applications requiring a regulated voltage output.

Abstract: A linear voltage regulator includes a voltage input and a voltage output. The linear voltage regulator includes a buffer having a voltage node, an input node, an output node and a control node and a power transistor having a control node coupled to the output node of the buffer, an input node coupled to the voltage input and an output node coupled to the voltage output. The linear voltage regulator includes a dropout detection module having a control node coupled to the control node of the power transistor, a voltage input node coupled to the voltage input, a voltage output node coupled to the voltage output and an output node. The linear voltage regulator includes a feedforward module having an input node coupled to the output node of the dropout detection module and an output node coupled to the control node of the buffer.

Abstract: A voltage regulation circuit includes a switching output terminal, a high-side output transistor, a low-side output transistor, a high-side replica transistor, a low-side replica transistor, and a comparator circuit. The high-side output transistor is configured to drive the switching output terminal. The low-side output transistor is configured to drive the switching output terminal. The high-side replica transistor is coupled to the high-side output transistor. The low-side replica transistor is coupled to the high-side replica transistor and the low-side output transistor. The comparator circuit is coupled to the high-side replica transistor and the low-side replica transistor, and is configured to compare a signal received from both the high-side replica transistor and the low-side replica transistor to a ramp signal.

Abstract: Methods and apparatuses for controlling an apparatus comprising a controller integrated in a first slave device. In an example, the controller can detect a sensed current of the first slave device. The controller can receive a voltage signal associated with a second slave device connected to the first slave device. The controller can generate a correction current based on the sensed current of the first slave device and the voltage signal. The controller can modulate a pulse width modulation (PWM) signal received by the first slave device using the correction current. The controller can control a power converter using the modulated PWM signal.

Abstract: Embodiments of an electrostatic discharge (ESD) protection device and a method for operating an ESD protection device are described. In one embodiment, an ESD protection device includes a primary ESD protection unit electrically connected to a first node and to a second node and configured to shunt current in response to an ESD pulse received between the first and second nodes and a secondary ESD protection unit electrically connected to the primary ESD protection unit and to the second node and configured to shunt current in response to the ESD pulse to keep an output voltage of the ESD protection device to be within a safe operating voltage range of a device to be protected. Other embodiments are also described.

Abstract: A reference voltage circuit is disclosed. In the reference voltage circuit, a comparator compares a reference voltage and a voltage of a capacitor, so as to output a comparison signal; a controller checks conditions of the reference voltage and the leakage current based on the comparison signal; when a voltage of the capacitor is reduced too quickly, the controller adjusts a switching frequency of a switch device to effectively maintain the voltage of the capacitor.

Abstract: A DLDO has a configuration that mitigates performance degradation associated with limit cycle oscillation (LCO). The DLDO comprises a clocked comparator, an array of power transistors, a digital controller and a clock pulsewidth reduction circuit. The digital controller comprises control logic configured to generate control signals that cause the power transistors to be turned ON or OFF in accordance with a preselected activation/deactivation control scheme. The clock pulsewidth reduction circuit receives an input clock signal having a first pulsewidth and generates the DLDO clock signal having the preselected pulsewidth that is narrower that the first pulsewidth, which is then delivered to the clock terminals of the clocked comparator and the digital controller. The narrower pulsewidth of the DLDO clock reduces the LCO mode to mitigate performance degradation caused by LCO.

Abstract: The invention relates to a circuit comprising a voltage reference (R) and a low-pass filter (F) electrically connected to the voltage reference (R). The filter (F) comprises a stage formed by a stage resistance (Re) electrically connected at a midpoint (M) to a stage capacitor (Ce), the stage resistance (Re) and the stage capacitor (Ce) at least partially defining a time constant of the filter and the midpoint (M) carrying the filtered reference voltage (V?ref). The circuit also comprises a transistor (T) and a control circuit (Cde) of the gate of the transistor (T) configured to bias the transistor (T) in conduction when the circuit (1) is turned on, the on-state resistance of the transistor (T) combining with the stage capacitor (Ce) to raise the filtered reference voltage (V?ref) with a settling time constant lower than the filter time constant.

Abstract: This disclosure describes systems, methods, and apparatus for reducing current imbalances between phases in a multi-phase converter as well as reducing instances of particular phases switching twice within a single pulse-width modulated cycle, or other time period. Phases that have not switched for a longest period of time can be compared to see if swapping their firing patterns would reduce current imbalances, and if so, then those firing patterns can be swapped.

Abstract: A method for regulating a voltage reference signal includes providing a first output current during a first interval and a boosted output current during a second interval to generate a low-dropout voltage reference signal based on a first power supply voltage, a second power supply voltage, and a reference voltage level. The method includes, during the second interval, compensating for a voltage drop caused by providing the boosted output current. The first output current may be provided in a first mode of operation. The boosted output current and voltage drop compensation may be provided in a boosted mode of operation.

Abstract: An apparatus includes first and second pluralities of switches, a controller for controlling these switches, gate-drivers for driving switches from the first plurality of switches, and first and second terminals configured for coupling to corresponding first and second external circuits at corresponding first and second voltages. During operation, the controller causes the first plurality of switches to transition between states. These transitions result in the second voltage being maintained at a value that is a multiple of the first voltage. The controller also causes the second plurality of switches to transition between states. These transitions resulting in capacitors being coupled or decoupled from the second voltage. The gate drivers derive, from the capacitors, charge for causing a voltage that enables switches from the first plurality of switches to be driven.

Abstract: A power manager circuit is provided. The power manager circuit includes a bandgap reference circuit, first and second monitoring circuits, and a reference buffer. The bandgap reference circuit generates a first voltage, based on an external voltage that is external to the power manager circuit. The first monitoring circuit determines a logical value of a first alarm signal, based on whether a first voltage level of the first voltage is within a first range. The reference buffer generates a second voltage, based on the first voltage. The second monitoring circuit determines a logical value of a second alarm signal, based on whether a second voltage level of the second voltage is within a second range.

Abstract: A multi-level inverter having at least two banks, each bank containing a plurality of low voltage MOSFET transistors. A processor configured to switch the plurality of low voltage MOSFET transistors in each bank to switch at multiple times during each cycle.

Abstract: An arrangement provides an AC current to a load for direct electrical heating. The arrangement includes a AC-DC-AC converter cell. The converter cell has at least two converter input terminals connected to at least two transformer output terminals. The converter cell has a first converter output terminal and a second converter output terminal, wherein the first converter cell output terminal is adapted to be connected to the load.

Abstract: An electronic system comprising a voltage-to-current converter and a proportional-to-absolute-temperature (PTAT) circuit is disclosed. The voltage-to-current converter is configured to receive one of a control voltage, a supply voltage, a scaled-down version of the control voltage, and a scaled-down version of the supply voltage, and generate a set of currents. The PTAT circuit is coupled with the voltage-to-current converter such that each current of the set of currents is one of sourced to the PTAT circuit and sank from the PTAT circuit. Further, the PTAT circuit is configured to receive at least one of the supply voltage and the control voltage, and generate a set of reference voltages. The control voltage is generated based on the set of reference voltages and the supply voltage.

Abstract: A method involves controlling, for a duration of a first modulation period, a first average off-time of a main switch of a power converter such that the first average off-time of the main switch corresponds to a first intermediate valley number of multiple intermediate valley numbers, an average of the intermediate valley numbers corresponding to a target number of valleys of a resonant waveform at a drain node of the main switch. A second intermediate valley number of the intermediate valley numbers is selected upon expiration of the first modulation period. A difference of the second intermediate valley number and the first intermediate valley number is equal to a fractional valley number offset. A second average off-time of the main switch is controlled for a duration of a second modulation period such that the second average off-time of the main switch corresponds to the second intermediate valley number.

Abstract: The present document relates to a power converter comprising an inductor, a first stage, and a second stage. The first stage may be coupled between an input of the power converter and the inductor, and the first stage may comprise a first flying capacitor. The second stage may be coupled between the inductor and an output of the power converter, and the second stage may comprise a second flying capacitor. A second terminal of the first flying capacitor may be connected to a first terminal of the inductor, and a first terminal of the second flying capacitor may be connected to a second terminal of the inductor.