Abstract: A dropout detection circuit for an LDO voltage regulator is disclosed. An LDO voltage regulator includes a power transistor having a drain terminal coupled to an output voltage node and a gate terminal coupled to an output of an error amplifier. A source terminal of the power transistor is coupled to an input voltage node. The circuit further includes a detection circuit having a first input coupled to the gate terminal and a second input coupled to the drain terminal. The detection circuit is configured to generate an indication responsive to detecting that the LDO voltage regulator has entered operation below a minimum dropout.

Abstract: For inductor-based DC-DC converters, a current shunt switch can provide an alternate path for the inductor current to flow that does not include the output capacitor. An amplifier circuit can be included and coupled with a control node of the current shunt switch to adjust a voltage on the control node to control an amount of inductor current diverted away from the output node. A fast linear loop can be included to ensure smooth transitions when engaging or disengaging the current shunt switch. These techniques can minimize the amount and duration of the subsequent negative output voltage excursion, which can be dependent on the specific ESL and ESR values of the output voltage capacitor, for the cases when the final value of the step-down load-transient is not zero. These techniques can improve a positive output voltage response caused by an output load transient in the negative direction.

Abstract: A bias circuit includes a linear core circuit CC with first and second mutually type corresponding transistors (M1; M2) and a current mirror CM with third and fourth transistors (M3; M4) of opposite type of M1 and M2. To obtain an equilibrium with a constant transconductance of the first transistor, first and second negative feedback loops (L1; L2) are applied, one including the linear core circuit CC, the other including the current mirror CM. In a first setting one loop suppresses differences between first and second drain voltages (Vd1; Vd2) and the other loop suppresses differences between one of of the first and second drain voltage Vd1 and Vd2 and a reference voltage Vref. In the second setting, one loop suppresses differences between the first drain voltage Vd1 and the reference voltage Vref and the other loop differences between the second drain voltage Vd2 and the reference voltage Vref.

Abstract: Circuits and methods that provide for fast power up and power down times in a multi-stage LDO regulator. In one embodiment, a multi-stage LDO regulator circuit includes, for each stage for which fast power up and/or power down times are desired, at least one transconductance amplifier coupled and configured to compare a primary reference voltage to one of a secondary reference voltage for the stage or an output voltage of the stage, and coupling and configuring the at least one transconductance amplifier to charge and/or discharge an associated capacitor to achieve a desired charge level within a specified time independently of the value of the associated capacitor. In general, the transconductance amplifiers of each stage are configured to charge and/or discharge an associated capacitor in synchronism with a voltage present on the primary reference voltage input.

Abstract: When a constant on-time flyback converter is in the switch-on stage, the gate voltage of the switch and the input voltage of the flyback converter adopt the primary side of the transformer to control. The gate voltage is controlled by the second control signal generated by the controller. The flyback converter is then turn off to enter the switch off stage. When the flyback converter is in the switch off stage, the secondary side controller on the secondary side of the transformer, based on the output voltage and output current of the secondary side, sends a first control signal to the primary side controller to control the main switch to turn on. Thus, the flyback converter enters the switch-on stage. Therefore, the calculation complexity is reduced, and there is no need to set a blanking time, such that the flyback converter can be used in high switching frequency applications.

Abstract: A switching regulator which has load transient quick response ability includes at least one power stage circuit and a control circuit. The control circuit includes a pulse width modulation (PWM) signal generation circuit and a quick response (QR) signal generation circuit. The PWM signal generation circuit generates a PWM signal according to an output voltage and a QR signal, to control a power switch of the corresponding power stage circuit, thus converting an input voltage to the output voltage. The QR signal generation circuit includes a differentiator circuit and a comparison circuit. The differentiator circuit performs a differential operation on a voltage sensing signal related to the output voltage, to generate a differential signal. The comparison circuit compares the differential signal with a QR threshold signal, such that when the differential signal exceeds the QR signal, the PWM signal generation circuit performs a QR procedure.

Abstract: In certain aspects, a voltage regulator includes a pass n-type field effect transistor (NFET) coupled between a first voltage rail and a second voltage rail, and a pass p-type field effect transistor (PFET) coupled between the first voltage rail and the second voltage rail. The voltage regulator also includes a first amplifier having an output, a first switch coupled between the output of the first amplifier and a gate of the pass NFET, a second amplifier having an output, and a second switch coupled between the output of the second amplifier and a gate of the pass PFET, a third switch coupled between the gate of the pass NFET and a ground, and a fourth switch coupled between the gate of the pass PFET and the second voltage rail.

Abstract: A startup circuit is provided. The startup circuit includes a first switch connected between an operating voltage terminal and a first connection node, and configured to perform a switching operation based on a shutdown signal, a second switch connected between the first connection node and ground, and configured to perform a switching operation based on a bandgap voltage, a logic circuit performing a logical AND operation on a first voltage of the first connection node and an enabling signal to generate a switching voltage, and a third switch connected between an output node and the ground, and configured to perform a switching operation based on the switching voltage, where the output node outputs a startup voltage.

Abstract: A power conversion system includes a power conversion circuit and a start circuit. The power conversion circuit includes a first terminal, a second terminal, an output capacitor, at switching unit, a flying capacitor and a magnetic element. The second switching unit includes two switch groups. The flying capacitor is connected between the first terminal and the second terminal. The magnetic element includes two first windings that are electromagnetically coupled with each other. A first one of the two first windings is electrically connected between one switch group and the second terminal of the power conversion circuit. A second one of the two first windings is electrically connected between the other switch group and the second terminal of the power conversion circuit. The start circuit includes a third winding, an inductor and at least one switch element. The third winding is electromagnetically coupled with the first windings.

Abstract: A switching power converter circuit may include output voltage overshoot mitigation circuitry that can modify operation of the converter responsive to an overvoltage condition by switching from a pulse width modulation (PWM) mode to a pulse frequency modulation (PFM) mode. A clamp may be provided to clamp a control voltage or a compensating capacitor voltage of the main output voltage control loop (e.g., a PWM control loop) to a control voltage of the PFM loop. An output pull down circuit may be provided to temporarily apply a load to the converter output.

Abstract: An electronic circuit includes a first transistor, a second transistor, and a variable resistor. The first transistor has a first threshold voltage. The second transistor has a second threshold voltage that is different from the first threshold voltage. The second transistor is coupled to the first transistor. The variable resistor is coupled to the first transistor and the second transistor. The variable resistor is configured to adjust a temperature coefficient of the electronic circuit. The electronic circuit is configured to generate a reference voltage based on a difference of the first threshold voltage and the second threshold voltage.

Abstract: A constant voltage device include a diode; a switch including one terminal connected to a ground potential and another terminal connected both to an anode terminal of the diode and to a drain of a PMOS transistor having a source applied with a power source voltage; a voltage generation circuit configured to generate a voltage of a predetermined magnitude; and a differential amplifier that includes a non-inverting input terminal to which both a cathode terminal of the diode and an output terminal of the voltage generation circuit are connected, and that is configured to change a supply route of a reference voltage applied to the non-inverting input terminal according to a state of the switch. The voltage generation circuit is configured to employ an output voltage based on the reference voltage and amplified by the differential amplifier to generate the reference voltage.

Abstract: A load coupled to a linear voltage regulator may create a load transient so that an output of the voltage regulator is temporarily raised to an elevated level above a regulated level. Without compensation, the linear voltage regulator may respond by turning a pass transistor completely OFF thereby losing regulation and allowing a compensation capacitor to become charged in a polarization opposite to one required for regulation. If a subsequent load transient (i.e., back-to-back load transient) is generated while the linear voltage regulator is in this condition, a large spike in the output may occur as the voltage regulator recharges the pass transistor turns back ON and as the compensation capacitor recharges. Disclosed herein is a linear voltage regulator with transient compensation circuitry to prevent the scenario described above and reduce the spike in the output.

Abstract: A multiphase switching converter has a plurality of switching circuits coupled in parallel, and a plurality of control circuits configured in a daisy chain. Each control circuit receives a phase input signal, and provides a phase output signal and a switching control signal for controlling a corresponding switching circuit. When a current sense signal is less than a phase shedding threshold, and if a corresponding one of the control circuits is a last one in the daisy chain or if a pulse on the phase input signal lasts within a preset time period, then a corresponding one of the switching circuits stops a power output, and the phase output signal equals the phase input signal.

Abstract: A method and an apparatus to provide bandgap calibration for multiple outputs are disclosed. In one implementation, a computing chip includes a bandgap current generator; a first adjustable current output coupled to the bandgap current generator; a second adjustable current output coupled to the bandgap current generator; a first switch selectively coupling the first adjustable current output to a calibration circuit and to a first analog-to-digital converter (ADC); and a second switch selectively coupling the second adjustable current output to a load on the computing chip and to the ADC.

Abstract: An all-MOSFET voltage reference circuit includes a first cascaded branch configured to generate a bias current and composed of a first current source and a diode-connected first N-type transistor connected at a first interconnected node; a second cascaded branch composed of a second current source, a diode-connected second N-type transistor and a third N-type transistor connected with the second N-type transistor disposed in between, wherein the second N-type transistor and the third N-type transistor are connected at a second interconnected node; a third cascaded branch composed of a third current source and a diode-connected fourth N-type transistor connected at an output node that provides a reference voltage; and an amplifier with a non-inverting node coupled to the first interconnected node and an inverting node coupled to the second interconnected node. A threshold voltage of the third N-type transistor is larger than a threshold voltage of the second N-type transistor.

Abstract: An adjuster includes a power transfer circuit, a negative feedback circuit, a constant current source circuit and a control circuit. Two inputs of an error amplifier in the negative feedback circuit receive a reference voltage and a feedback voltage corresponding to an output signal of the adjuster respectively, and the error amplifier is configured to output a first voltage signal when the feedback voltage is less than the reference voltage, and output a second voltage signal when the feedback voltage is greater than the reference voltage, during the starting process of the adjuster. The control circuit is configured to control the negative feedback circuit to be turned off and the constant current source circuit to be turned on, and control the constant current source circuit to be turned off and the negative circuit to be turned on according to the second voltage signal.

Abstract: A method for limiting an input or output current of a DC-DC converter and a current limiting circuit are disclosed. In an embodiment a method for limiting an input or output current of a DC to DC converter includes storing a first value representative of a level of an output voltage of the DC to DC converter in response to the input or output current exceeding or falling below a first threshold and modifying a control signal based on the first value.

Abstract: An example apparatus includes power amplification circuitry and current-level switch circuitry. The power amplification circuitry has a first input port, a second input port, and field-effect transistor (FET) circuitry, the FET circuitry to operate in a saturation mode while drawing power provided at the first input port from a first power source. The current-level switch circuitry is to sense a change in a current-level used to maintain the FET circuitry in the saturation mode and, in response to the sensed change in the current-level, to cause the power amplification circuitry to draw power provided at the second input port from a second power source while maintaining the saturation mode of the FET circuitry.

Abstract: A multi-level inverter having one or more banks, each bank containing a plurality of low voltage MOSFET transistors. A processor configured to switch the plurality of low voltage MOSFET transistors in each bank to switch at multiple times during each cycle.