Abstract: An apparatus includes a first encoder circuit configured to compress a block of data using dictionary based compression and a second encoder circuit connected to the first encoder circuit to receive the compressed block of data from the first encoder circuit. The second encoder circuit is configured to further compress the compressed block of data according to a codebook. The codebook is based on a distribution of data of a prior block of data or a distribution of data of a portion of the block of data that is less than the block of data. The operation of the second encoder circuit overlaps with the operation of the first encoder circuit to achieve high throughput and avoid the need for a large block of memory (e.g., SRAM) to occupy the data in flight until the second encoder circuit can start.

Abstract: An apparatus may include a first clock generator configured to receive an input clock signal, and generate two or more first-level clock signals of a track-and-hold circuit, a phase interpolator configured to generate an interpolated clock signals, wherein the interpolated clock signal is based on the two or more first-level clock signals, and a second clock generator configured to generate two or more second-level clock signals based on the interpolated clock signal, wherein the phase of the two or more second-level clock signals relative to the phase of a respective first-level clock signal is determined, at least in part, by the phase of the interpolated clock signal.

Abstract: The A/D converter includes a D/A conversion circuit configured to perform a D/A conversion on a DAC input digital value to output a DAC output signal, a difference output circuit for outputting difference signals based on a difference between the input signal and the DAC output signal, an A/D conversion circuit for performing an A/D conversion on the difference signals to output an ADC output digital value, and a control circuit for outputting the DAC input digital value based on the ADC output digital value. The control circuit outputs a first DAC input digital value and a second DAC input digital value different from the first DAC input digital value, and obtains ADC result data based on a first ADC output digital value obtained in accordance with the first DAC input digital value, a second ADC output digital value obtained in accordance with the second DAC input digital value, and the DAC input digital value.

Abstract: Certain aspects are directed to an apparatus configured for wireless communication. The apparatus may include a memory comprising instructions, and one or more processors configured to execute the instructions. In some examples, the one or more processors are configured to cause the apparatus to obtain a sample of an analog signal. In some examples, the one or more processors are configured to cause the apparatus to output the sample to an analog-to-digital converter (ADC) via one of at least a first path or a second path based at least in part on whether the sample satisfies a first threshold condition or a second threshold condition.

Abstract: An integrated circuit includes a continuous time delta sigma analog-to-digital converter (CTDS ADC) and a test circuit for testing the CTDS ADC. The test circuit converts multi-bit digital reference data to a single-bit digital stream. The test circuit then passes the single-bit digital stream to a finite impulse response digital-to-analog converter (FIR DAC). The FIR DAC converts the single-bit digital stream to an analog test signal. The analog test signal is then passed to the CTDS ADC. The CTDS ADC converts the analog test signal to digital test data. The test circuit analyzes the digital test data to determine the accuracy of the CTDS ADC.

Abstract: Techniques for facilitating analog-to-digital converter calibrations are provided. In one example, a method includes, for each of a plurality of time instances, generating a first ramp signal started at the time instance relative to a respective start of a first counter signal and generating a respective comparator output signal based on the first ramp signal and a first threshold signal. The method further includes capturing a respective first value of the first ramp signal in response to a transition of the respective comparator output signal. The method further includes determining a respective second counter value of a second counter signal based on the respective first value. The method further includes determining a scaling factor based on the second counter values and the time instances. Each of the first values is associated with the same counter value of the first counter signal. Related devices and systems are also provided.

Abstract: An electronic device includes a bracket including a first structure at least partially having non-conductivity, a second structure disposed on a first surface of the first structure and at least partially having conductivity, and an antenna pattern electrically connected with the second structure and disposed on a second surface of the first structure, and a printed circuit board including a grounding part and a feeding part. The grounding part is electrically connected with the second structure, and the feeding part is electrically connected with a portion of the antenna pattern.

Abstract: A semiconductor integrated circuit according to an embodiment includes an A/D converter, first and second equalizer circuits, and first and second controllers. The first equalizer circuit includes a first tap. The first and second equalizer circuits receive a signal based on a digital signal, and output first and second signals, respectively. The first controller adjusts a phase of a clock signal based on the first signal. The second controller an operation of adjusting a control parameter including a tap coefficient. In the operation, the second controller adjusts a tap coefficient of each of taps of the second equalizer circuit, and adjusts a tap coefficient of the first tap based on an adjustment result of each tap coefficient of the second equalizer circuit.

Abstract: An antenna apparatus is disclosed, including a lower housing, a middle housing disposed on the lower housing and having one surface formed with one or more first heat dissipation fins, a first accommodation space formed by the lower housing and the middle housing, at least one first heat-generating element disposed in the first accommodation space, one or more heat dissipation supports each disposed on the middle housing and having at least one surface formed with one or more second heat dissipation fins, and an antenna module supported on the one or more heat dissipation supports.

Abstract: A background offset calibration system for an analog signal comparator provides low offset without compromising tracking bandwidth. The comparator includes a preamplifier and a decision latch. A switching selectively couples outputs of an analog circuit to the inputs of the preamplifier stage. A state control logic alternatively operates the system in a first phase in which the analog circuit acquires an input signal while the comparator is calibrated, and a second phase in which a comparison is performed by the comparator. In the first phase, the switching circuit disconnects the outputs of the analog circuit from the preamplifier stage and applies a common mode reference to the inputs of the preamplifier. An offset correction circuit determines correction changes from a history of states of the decision latch across multiple sampling cycles. The offset correction circuit adjusts a threshold voltage of the decision latch by applying the correction changes.

Abstract: In described examples, a circuit includes a calibration engine. The calibration engine generates multiple input codes. A digital to analog converter (DAC) is coupled to the calibration engine, and generates a first calibration signal in response to a first input code of the multiple input codes. An analog to digital converter (ADC) is coupled to the DAC, and generates multiple raw codes responsive to the first calibration signal. A storage circuit is coupled to the ADC and stores a first output code corresponding to the first input code. The first output code is obtained using the multiple raw codes generated by the ADC.

Abstract: An electronic device according to various embodiments of the present disclosure can comprise: a front plate facing a first direction; a rear plate facing a second direction, which is opposite to the first direction; at least one antenna module arranged between the front plate and the rear plate; and at least one heat dissipation sheet spaced from the at least one antenna module so as to be arranged to come in contact with the rear plate. The at least one heat dissipation sheet can comprise a ceramic filler and a binder resin mixed with the ceramic filler.

Abstract: An apparatus comprises circuitry configured to generate a predicted error signal by applying to a digital signal a distortion model characterized by parameters configured to model circuit component mismatches in a digital-to-analog converter (DAC), circuitry configured to generate a pre-compensated digital signal using the digital signal and the predicted error signal, and circuitry configured to provide the pre-compensated digital signal to the DAC for conversion into an analog signal.

Abstract: Systems and methods are provided for analog-to-digital conversion (ADC). A first quantization stage may be configured to receive an analog input signal and sample the analog input signal to generate a first digital signal, the first quantization stage may be further configured to filter the first digital signal with a first noise-shaping transfer function to generate a first noise-shaped digital output and to generate a quantization error signal based on a comparison of the analog input signal and the first noise-shaped digital output. A voltage controlled oscillator (VCO)-based second quantization stage may be configured to receive the quantization error signal and sample the quantization error signal to generate a second digital signal, the VCO-based second quantization stage may be further configured to filter the second digital signal with a second noise-shaping transfer function to generate a second noise-shaped digital output.

Abstract: Systems and methods are related to a successive approximation analog to digital converter (SAR ADC). The SAR ADC includes a sample and digital to analog conversion (DAC) circuit configured to sample an input voltage, a comparator circuit coupled to the sample and DAC circuit and having an output, a first set of storage circuits, and a comparator driver. The comparator driver is disposed between the output and the first set of storage circuits (e.g., ratioed latched. The first set of storage circuits are coupled to the comparator circuit and the sample and DAC circuit. The comparator driver can include a first driver and second driver. The first driver is coupled to a first input of a first storage circuit of the first set of storage circuits, and the second driver is coupled to first inputs of a second set of storage circuits within the first set of storage circuits.

Abstract: Described herein is a data processing system having a multisample antialiasing compressor coupled to a texture unit and shader execution array. In one embodiment, the data processing system includes a memory device to store a multisample render target, the multisample render target to store color data for a set of sample locations of each pixel in a set of pixels; and general-purpose graphics processor comprising a multisample antialiasing compressor to apply multisample antialiasing compression to color data generated for the set of sample locations of a first pixel in the set of pixels and a multisample render cache to store color data generated for the set of sample locations of the first pixel in the set of pixels, wherein color data evicted from the multisample render cache is to be stored to the multisample render target.

Abstract: Embodiments herein describe a capillary containing a eutectic conductive liquid (e.g., EGaIn) and an electrolyte (e.g., NaOH) that is integrated into a printed circuit board (PCB). In one embodiment, the PCB includes a capillary, a negative electrode, a positive electrode, a plurality of insulation layers, and a conductive layer. The capillary extends through the PCB. The capillary includes a side surface forming an annular cylinder. A eutectic conductive liquid and an electrolyte are disposed within an aperture formed by the side surface. An electrode extends through the side surface and contacts at least the eutectic conductive liquid or the electrolyte. The negative electrode is disposed at a first end of the capillary. The positive electrode is disposed at a second end of the capillary. The conductive layer is disposed between two of the plurality of insulation layers. The electrode forms an electrical connection with the conductive layer.

Abstract: A multiplier is configured to implement multiplication of a first value of M bits and a second value of N bits, and includes P groups of encoders and W layers of inversion compressors. Each group include N encoders and are configured to encode a part of bits in the second value, and a group selection signal and a symbol control input signal corresponding to the each group. The group selection signal and the symbol control input signal are generated based on a part of bits in the first value, and the P groups of encoders perform encoding to obtain P partial products. The W layers of inversion compressors are configured to compress the P partial products.

Abstract: Embodiments of the present disclosure include a digital circuit and method for compressing input digital values. A plurality of input digital values may include zero values and non-zero values. The input digital values are received on M inputs of a first switching stage. The first switching stage is arranged in groups that rearrange the non-zero values on first switching stage outputs according to a compression and shift. The compression and shift position the non-zero values on outputs coupled to inputs of a second switching stage. The second switching stage consecutively couples non-zero values to N outputs, where N is less than M.

Abstract: A system and method for faster communication between blockchain mining nodes and faster block validation. The system uses machine learning on data chunks to generate codebooks which compact the data to be stored, processed, or sent with a smaller data profile than uncompacted data. The system uses a data compaction in an existing blockchain fork or implemented in a new blockchain protocol from which nodes that wish to or need to use the blockchain can do so with a reduced storage requirement. The system uses network data compaction across all nodes to increase the speed of and decrease the size of a blockchain's data packets. The system uses data compaction firmware to increase the efficiency at which mining rigs can computationally validate new blocks on the blockchain. The system can be implemented using any combination of the three data compaction services to meet the needs of the desired blockchain technology.