Abstract: A receiver circuit includes an interleaved ADC, a first delay circuit, a second delay circuit, a first processing channel, a second processing channel, and an interleaving ADC timing error detector circuit. The interleaved ADC includes a first ADC and a second ADC in parallel. The first delay circuit delays a first clock signal provided to the first ADC. The second delay circuit delays a second clock signal provided to the second ADC. The first processing channel processes data samples provided by the first ADC, and includes a first slicer. The second processing channel processes data samples provided by the second ADC, and includes a second slicer. The interleaving ADC timing error detector circuit controls delay of the first delay circuit and the second delay circuit based on an output signal of the first slicer, and an output signal or an input signal of the second slicer.

Abstract: There is provided a computer-implemented method of compressing a baseline dataset, comprising: creating a weight function that calculates a weight for each instance of each unique data elements in the baseline dataset, as a function of sequential locations of each of the instances of each respective unique data element within the baseline dataset, creating an output dataset storing a codeword for each one of the unique data elements, wherein codewords are according to a compression rule defining data elements associated with a relatively higher weight as being associated with codewords that are relatively shorter, dynamically creating the compressed dataset by sequentially iterating, for each current sequential location of the baseline dataset: determining an encoded data element mapped to the respective data element of the current sequential location according to the weight function, and adjusting the codewords of the output dataset according to the current weights to maintain the compression rule.

Abstract: An antenna device configured to be attached to a vehicle includes: an antenna of a resonance type; and a matching circuit connected to the antenna, wherein the matching circuit includes a first matching circuit connected to a feeding portion of the antenna and a second matching circuit connected to a subsequent stage of the first matching circuit, wherein the first matching circuit reduces an impedance in a frequency band that is away to a higher-frequency range or a lower-frequency range from a resonance point of the antenna such that the impedance is lower than before connection of the first matching circuit, and the second matching circuit increases an impedance in a vicinity of the resonance point of the antenna such that the impedance is higher than before connection of the second matching circuit.

Abstract: Methods and systems for encoding and decoding data, such as point cloud data. The methods may include using a coder map to map a range of discrete dependency states to a smaller set of binary coders each having an associated coding probability. The selection of one of the discrete dependency states may be based on a contextual or situational factors, which may include a prediction process, for a particular symbol, such as an occupancy bit. The coder map is updated after each symbol is coded to possibly alter to which binary coder the selected discrete dependency state maps.

Abstract: An antenna includes at least one antenna element mounted on a substrate and extending normally thereto. The at least one antenna element is constructed from a plurality of antenna components, one of which is an upper antenna component that is furthest from the substrate. A support material surrounds the at least one antenna element and is disposed between the antenna components. A material layer is disposed on the upper antenna component and the support material. Heating elements may be interposed between the upper antenna component and the material layer, and an additional material layer, such as an ablative layer, may be disposed on the material layer.

Abstract: There is provided a combined antenna and radome arrangement. The combined antenna and radome arrangement comprises an advanced antenna system (AAS). The AAS comprises antenna elements and is configured for communication in a frequency range of 2.5 GHz to 10 GHz. The combined antenna and radome arrangement further comprises a radome. The radome has a first layer sandwiched between two second layers. The two second layers are of a second dielectric material. The first layer is of a first dielectric material and has a thickness t1, where t1??min/3, wherein ?min is the wavelength of the highest frequency in the frequency range of the AAS. The radome is placed in front of the AAS such that the radome forms a cover for the AAS.

Abstract: A compression engine calculates replacement CRC codes, in predetermined data lengths, for DIF-in cleartext data including cleartext data and multiple CRC codes based on the cleartext data. The compression engine generates headered compressed-text data in which a header including the replacement CRC codes is added to compressed-text data in which the cleartext data is compressed, and generates code-in compressed-text data by calculating multiple CRC codes based on the headered compressed-text data to add the calculated CRC codes to the headered compressed-text data.

Abstract: This application provides examples of a base station antenna, a switch, and a base station device. A connection status between an output port and an input port of a horizontal-dimensional feeding network is changed by using a switch of the horizontal-dimensional feeding network. In different connection statuses, quantities of input ports that are connected to a plurality of output ports of the horizontal-dimensional feeding network are different. The input port of the horizontal-dimensional feeding network is in communication with an antenna port to form a transceiver channel. In this case, a quantity of transceiver channels, of the horizontal-dimensional feeding network, formed in each connection status is different. Therefore, the quantity of transceiver channels supported by the base station device can be changed by using the base station antenna without a need of replacing the base station antenna.

Abstract: The present invention includes: a first decoder that outputs mutually different two voltages as first and second selection voltages based on a first bit group of a digital data signal in a first selection state, and outputs one or both of the two voltages as the first and the second selection voltages in a second selection state; a second decoder that outputs mutually different two voltages as third and fourth selection voltages based on a second bit group of the digital data signal in the first selection state and outputs one voltage based on the second bit group as the third and the fourth selection voltages in the second selection state; and an amplifier circuit that averages a combination of the first and the second selection voltages or the third and the fourth selection voltages with predetermined weighting ratios and outputs the averaged voltage.

Abstract: An antenna element comprises a housing having a base and a conducting plate, and a feeding element. The housing has a cavity formed between the base and the conducting plate. The conducting plate has a radiating slot with a length and a width that extends longitudinally along a first axis and a second axis, respectively. The radiating slot has a first and a second edge along the first axis. The feeding element has a feeding point, a feeding line, and a stub. The feeding line extends along the second axis of the conducting plate across the width of the radiating slot such that a first end of the feeding line is coupled with the feeding point on one side of the radiating slot, and a second end of the feeding line extends past the second edge, and the stub extends laterally of the feeding line.

Abstract: The invention relates to an analog-to-digital converter (ADC). The objective of the invention to have an analog-to-digital converter with the capability of non-equidistant sample time spacing and minimizing energy consumption will be solved by an apparatus comprising a sigma-delta modulator and a sample-time-counter, both controlled by a sample clock, a next-sample-time-computation unit configured to compute a sample-time-counter value when a next digital output sample is requested, a sample-computation-trigger unit connected to the next-sample-time-computation unit configured to compare an actual sample-time-counter value with the sample-time-counter value when the next digital output sample is requested and to trigger a computation unit for calculating a next digital sample when requested and by powering off the sigma-delta modulator in intervals where its delivered samples are not used for any computed decimator output sample.

Abstract: A stream decompression circuit is disclosed. The stream decompression circuit includes a coding length first-in-first-out (FIFO) and a calculation circuit. The coding length FIFO is coupled to a variable length coding (VLC) circuit and used to store a coding length that the VLC circuit codes sub-streams and output a specific number of bits when the coding length accumulates over the specific number of bits. The calculation circuit is coupled between the coding length FIFO and a multiplexer circuit and used to calculate a number of bits required for decompression and output an output multiplex control signal to the multiplexer circuit to control the multiplexer circuit to output the sub-streams according to a specific order.

Abstract: An apparatus and method for analog to digital conversion of analog input signals are disclosed herein. In some embodiments, an analog-to-digital (ADC) may comprise: a first successive approximation register (SAR) circuit comprising a fast SAR (FSAR) circuit and a residue digital-to-analog converter (RDAC) circuit and a residue amplifier circuit, coupled to the RDAC circuit, comprising an amplifier circuit that is configured to amplify a residual signal generated by the RDAC circuit, wherein the amplifier circuit comprises a deadzone control circuit and a first, second and third inverter stages, wherein the third stage is biased to operate in a sub-threshold region.

Abstract: A pulse width modulation (PWM) digital-to-analog conversion circuit includes switches 102, 104, 114, 116 controlled by a first PWM signal, and switches 106, 108, 110, 112 controlled by a second PWM signal. A first operational amplifier (op-amp) includes a first input coupled to an output of a filter, and a second input coupled to an output of the first op-amp. During a first time period, an output of a second op-amp is coupled to an input of the filter via switches 102 and 104, and an output of a third op-amp is coupled to the output of the first op-amp via switches 114 and 116. During a second time period, the output of the second op-amp is coupled to the output of the first op-amp via switches 106 and 108, and an output of the third op-amp is coupled to the input of the filter via switches 110 and 112.

Abstract: Lossy methods and hardware for compressing data and the corresponding decompression methods and hardware are described. The lossy compression method comprises dividing a block of pixels into a number of sub-blocks and then analysing, for each sub-block, and selecting one of a candidate set of lossy compression modes. The analysis may, for example, be based on the alpha values for the pixels in the sub-block. In various examples, the candidate set of lossy compression modes comprises at least one mode that uses a fixed alpha channel value for all pixels in the sub-block and one or more modes that encode a variable alpha channel value.

Abstract: A vehicular antenna device includes an antenna portion having an antenna element, and a frame accommodating a heat generation member. The vehicular antenna device is configured to be attached to an attachment portion of a vehicle. The frame includes a first space portion having a cylindrical shape and defining a first space, the first space portion being exposed to an outside air in a condition where the vehicular antenna device is attached to the vehicle. The heat generation member is located along a second surface of the frame that is a reverse side of a first surface defining the first space. The antenna portion is detachable from the frame.

Abstract: Systems and methods for an asynchronous successive approximation register analog-to-digital converter (SAR ADC) with word completion algorithm may include a SAR ADC comprising a plurality of switched capacitors, a comparator, a metastability detector including a timer having a tunable time interval, and a successive approximation register. The SAR ADC may sample input signals at inputs of the switched capacitors; compare signals at outputs of the switched capacitors, each for a respective bit; sense whether a metastability condition exists for the comparator using the timer and setting a metastability flag upon each metastability detection for each bit; increase a value of the tunable time interval if more than one metastability flag is set during conversion of a sampled input signal; decrease a value of the tunable time interval if no metastability flags are set; and use the flags for a word completion in the cases when not all the bits have been evaluated.

Abstract: An analog-to-digital converter, ADC, module is configured to operate in a coarse conversion ADC phase, and a fine conversion ADC phase comprising a delta modulation loop for tracking a signal, wherein the ADC module is configured to, at initiation of input of an analog signal, operate in the coarse conversion ADC phase for determining a coarse digital value; wherein the ADC module is configured to, when the coarse digital value is determined, operate in the fine conversion ADC phase, receive the coarse digital value as an initial approximation of the analog signal and track the analog signal during a finite duration.

Abstract: The preset invention relates to a dual polarized antenna and an antenna array and, more particularly, to a dual polarized antenna comprising: a top portion having a radiation patch; a bottom portion forming a probe; and side portions formed along the outer peripheral edge of the top portion so as to have a predetermined height, wherein the side portions include a cup-shaped aluminum structure, and the top portion, the bottom portion, and the side portions are formed in an integrated form.

Abstract: A multiband antenna has a plurality of first, unit cells and second unit cells. Each first unit cell has two high band radiator clusters and two low band radiators disposed approximately in the center of each of the high band radiator clusters. Each second unit cell has two high band radiator clusters and one low band radiator that is disposed between the two high band radiator clusters. The first unit cell is designed for a superior low band gain pattern, and the second unit cell is designed for a superior high band gain pattern. By selectively arranging the first and second unit cells in a specific heterogeneous pattern, the characteristics of the two unit cells may advantageously and constructively combine to form a high performance antenna gain pattern that is consistent across the low band and high band.