Abstract: A digital conversion system including a sigma-delta converter, a signal generator providing a substantially symmetrical injection signal that is injected into the sigma-delta converter conversion path, bandpass filters for filtering the injection signal and the output of the sigma-delta converter, a correlator that correlates the filtered signals for providing an error signal, and a loop controller that uses the error signal to adjust a resonant frequency of the sigma-delta converter to output a target notch frequency. The loop controller may adjust a resonant frequency of a loop filter of the sigma-delta converter, in which the bandpass filters may each be centered at the target notch frequency at the output of the sigma-delta converter. The correlator may include a complex conjugate block, a multiplier and a mean calculator. The loop controller may include a converter and an amplifier and an integrator or a least-mean square block.

Abstract: A passive sigma-delta modulator including first modulator loop, a second modulator loop, and a digital combiner providing an output signal. The first modulator loop includes a first quantizer, a first passive summing junction, a first continuous-time passive analog loop filter, and a first feedback path. The second modulator loop includes a second quantizer, analog transfer circuitry, a second continuous-time passive summing junction, a second passive analog loop filter, a second feedback path, and digital transfer circuitry having a gain that is substantially a reciprocal of the analog transfer circuitry. A digital noise cancelation filter may be located between the first quantizer and the digital combiner, or an analog noise cancelation filter may be provided within the second modulator loop. Single-ended or differential configurations are contemplated.

Abstract: An apparatus of neural network model decompression includes processing circuitry. The processing circuitry can be configured to receive, from a bitstream of a compressed neural network representation, one or more first syntax elements associated with a 3-dimensional coding unit (CU3D) partitioned from a 3-dimensional coding tree unit (CTU3D). The first CTU3D can be partitioned from a tensor in a neural network. The one or more first syntax elements can indicate that the CU3D is partitioned based on a 3D pyramid structure that includes multiple depths. Each depth corresponds to one or more nodes. Each node has a node value. Second syntax elements corresponding to the node values of the nodes in the 3D pyramid structure can be received from the bitstream in a breadth-first scan order for scanning the nodes in the 3D pyramid structure. Model parameters of the tensor can be reconstructed based on the received second syntax elements.

Abstract: One or more systems and/or methods for implementing an analog-to-digital converter system with a floating digital channel configuration are provided. An analog input component is configured to receive measured analog signals, and output analog signals, corresponding to the measured analog signals, to an analog channel coupled to the analog input component. The analog channel is coupled to a switching component connected to a first digital channel and a second digital channel. The analog channel comprises a modulator configured to convert the analog signals into a data stream selectively input by the switching component to the first digital channel or the second digital channel.

Abstract: Digital-to-analog converter (DAC) architecture, comprising: a matrix DAC array comprising a plurality of cells arranged in a first dimension and a second dimension, each cell comprising a local decoder configured to transition the cell between at least two states; and decoding circuitry configured to: receive a digital input signal; and control the plurality of local decoders based on a received digital input signal, wherein each incremental change in the digital input signal results in a transition of a single cell of the plurality of cells such that the plurality of cells transition in sequence, the sequence of transitions of the plurality of cells defining a path through the DAC array; wherein when the path proceeds in the first dimension, the path proceeds to an adjacent cell of the plurality of cells at least 50% of the time; and wherein when the path proceeds in the second dimension, the path proceeds to an adjacent cell of the plurality of cells at least 50% of the time.

Abstract: Methods, apparatus, systems, and software for implementing self-checking compression. A byte stream is encoded to generate tokens and selected tokens are encoded with hidden parity information in a compressed byte stream that may be stored for later streaming or streamed to a receiver. As the compressed byte stream is received, it is decompressed, with the hidden parity information being decoded and used to detect for errors in the decompressed data, enabling errors to be detected on-the-fly rather than waiting to perform a checksum over an entire received file. In one embodiment the byte stream is encoded using a Lempel-Ziv 77 (LZ77)-based encoding process to generate a sequence of tokens including literals and references, with all or selected references encoded with hidden parity information in a compressed byte stream having a standard format such as DEFLATE or Zstandard.

Abstract: An apparatus includes a processor and a machine-readable medium having program code to cause the apparatus to obtain a first dictionary based on a first training set of signals and determine a first subset of the first training set of signals based on a training reconstruction accuracy threshold and the first dictionary, wherein each atom in the first dictionary includes at least one of a signal pattern and a function representing the signal pattern. The program code also includes code to generate a second dictionary based on a second training set of signals, wherein the second training set of signals includes the first subset of the first training set of signals.

Abstract: A method for transmitting information using a pulse may comprise transmitting, via a channel between a first device and a second device, an idle state for an idle time; and transmitting, via the channel, a pulse state for a pulse time, wherein the idle time and the pulse time define a value for a data word being transmitted, and wherein the duration of one or more of the idle time and the pulse time vary depending upon the value of the data word.

Abstract: An electronic apparatus is provided. The electronic apparatus includes a storage storing a matrix included in an artificial intelligence model, and a processor. The processor divides data included in at least a portion of the matrix by one of rows and columns of the matrix to form groups, clusters the groups into clusters based on data included in each of the groups, and quantizes data divided by the other one of rows and columns of the matrix among data included in each of the clusters.

Abstract: A resolver signal processing apparatus processes a resolver signal output from a resolver by applying an excitation signal generated by an excitation signal generating unit. In particular, the resolver signal processing apparatus includes: a resolver signal processing unit, in which the resolver signal processing unit includes a resolver signal acquiring unit receiving the resolver signal and extracting pole information of the resolver signal, a resolver phase compensating unit compensating a pole acquisition time of extracting the pole information of the resolver signal acquiring unit, and a resolver-digital converter outputting a digital signal by using the pole information extracted from the resolver signal acquiring unit, and a resolver signal processing method using the same.

Abstract: The disclosure provides a look-up table (LUT) compression method and a LUT reading method for computation equipment and its host and device. In a LUT compression phase, the host retrieves an original data from an original LUT by using an original table address, checks the original data according to a reconstruction condition to obtain a check result (bitmap), converts the original data into a reconstructed data according to the check result, writes the reconstructed data to a compressed LUT by using a compressed table address, writes a relationship among the original table address, the compressed table address, and the check result (bitmap) to a mapping table, and stores the compressed LUT to the device.

Abstract: In an embodiment a method for operating a gas sensor arrangement includes generating a sensor current by a gas sensor, converting the sensor current into a digital comparator output signal in a charge balancing operation depending on a first clock signal, determining from the digital comparator output signal an asynchronous count comprising an integer number of counts depending on the first clock signal, determining from the digital comparator output signal a fractional time count depending on a second clock signal and calculating from the asynchronous count and from the fractional time count a digital output signal which is indicative of the sensor current generated by the gas sensor.

Abstract: A metastable state detection device and method, and an ADC circuit are disclosed. The metastable state detection device includes: a delay unit which is configured to receive a synchronization signal and delay the synchronization signal based on preset step delay values; a first flip-flop unit including a first clock input terminal, a first data input terminal and a first data output terminal, wherein the first clock input terminal is configured to receive a clock signal; the first data input terminal is configured to receive the delayed synchronization signal; a second flip-flop unit including a second clock input terminal, a second data input terminal and a second data output terminal; a processing module connected to the second data output terminal, which is configured to receive a target clock signal and detect a metastable state of the first flip-flop unit according to the target clock signal.

Abstract: A time interleaved analog-to-digital converter (TIADC) is provided. The TIADC converts an input signal into a digital output signal and includes N analog-to-digital converters (ADCs), a clock generation circuit, and a control circuit. The N ADCs receive the input signal and sample the input signal according to N sampling clocks to each generate a digital output code, N being an integer greater than or equal to 2. The clock generation circuit is configured to receive a working clock and a set of control values and to generate the N sampling clocks according to the set of control values and the working clock. The control circuit is configured to periodically generate the set of control values based on a pseudo random number and to output the digital output codes in turn as the digital output signal.

Abstract: A delta-sigma modulator includes a first amplifier having an input, a feedback control input, and an output. The input is a first input of the delta-sigma modulator. The delta-sigma modulator further includes a first integrator and a first quantizer. The first integrator has an input and an output. The output of the first amplifier is coupled to the input of the first integrator. The first quantizer has an input and an output. The output of the first quantizer is coupled to the feedback control input of the first amplifier.

Abstract: Disclosed are a system and a battery management integration circuit using an incremental analog-to-digital converter (ADC), which can reduce the consumption of the amount of a bias current. The system includes an incremental ADC configured to perform accumulation on an analog signal during an oversampling period and a bias current generator configured to provide a bias current for the accumulation of the incremental ADC. The bias current generator provides a first amount of the bias current in a first period defined from start timing of oversampling to preset timing during the oversampling period, and provides a second amount of the bias current, smaller than the first amount of the bias current, in a second period subsequent to the first period.

Abstract: An analog-to-digital converter (“ADC”) includes an input terminal configured to receive an analog input signal. A first ADC circuit is coupled to the input terminal and includes a VCO. The first ADC circuit is configured to output a first digital signal in a frequency domain based on the analog input signal. The first digital signal includes an error component. A first DAC is configured to convert the first digital signal to an analog output signal. A first summation circuit is configured to receive the analog output signal, the analog input signal, and a loop filtered version of the analog input signal and extract the error component, and output a negative of the error component. A second ADC circuit is configured to convert the negative of the error component to a digital error signal. A second summation circuit is configured to receive the first digital signal and the digital error signal, and to output a digital output signal corresponding to the analog input at an output terminal.

Abstract: This application describes method and apparatus for data conversion. An analogue-to-digital converter circuit receives an analogue input signal (SIN) and outputs a digital output signal (SOUT). The circuit has a sampling capacitor, a controlled oscillator and a counter for generating a count value based on a number of oscillations in an output of the controlled oscillator in a count period during a read-out phase. The digital output signal is based on the count value. The converter circuit is operable in a sampling phase and the read-out phase. In the sampling phase, the sampling capacitor is coupled to an input node for the input signal, e.g. via switch. In the read-out phase, the sampling capacitor is coupled to the controlled oscillator, e.g. via switch, such that capacitor powers the first controlled oscillator and a frequency of oscillation in the output of the first controlled oscillator depends on the voltage of the first capacitor.

Abstract: A device is provided comprising a first oscillator based analog-to-digital converter configured to receive an analog input signal and output a first digital signal and a second oscillator based analog-to-digital converter configured to receive an analog reference signal and output a second digital signal. The device further comprises output logic configured to generate a digital output signal based on the first digital signal and the second digital signal.

Abstract: A mobile communication antenna comprises a radome, a reflector arrangement, mobile communication radiators, and at least one electronic module. The radiators are arranged on a front side and the at least one electronic module is arranged on a rear side of the reflector arrangement. At least one electronic module comprises an electronic unit and a module housing within which the electronic unit is arranged. The module housing is made of metal and comprises a front side, a rear side, end faces and side walls, wherein the front side of the module housing points in the direction of the radome and the rear side of the module housing points in the direction of the rear side of the reflector arrangement. At least the surface of the front side and/or the rear side of the module housing is at least predominantly coated with a heat emission layer.