Abstract: An electronic device is provided and includes a first electrode, a second electrode and a photoelectric conversion layer sandwiched between the first electrode and the second electrode, the first electrode including an amorphous oxide including a quaternary compound including one or more of indium, gallium and aluminum and further including zinc and oxygen, the first electrode having a laminated structure including a first B layer and a first A layer from a photoelectric conversion layer side, and a work function value of the first A layer of the first electrode being lower than a work function of the first B layer of the first electrode.

Abstract: Embodiments described herein include electronic packages and methods of forming such packages. An electronic package includes a package substrate, first conductive pads formed over the package substrate, where the first conductive pads have a first surface area, and second conductive pads over the package substrate, where the second conductive pads have a second surface area greater than the first surface area. The electronic package also includes a solder resist layer over the first and second conductive pads, and a plurality of solder resist openings that expose one of the first or second conductive pads. The solder resist openings of the electronic package may include conductive material that is substantially coplanar with a top surface of the solder resist layer. The electronic package further includes solder bumps over the conductive material in the solder resist openings, where the solder bumps have a low bump thickness variation (BTV).

Abstract: The present disclosure provides a semiconductor device, a semiconductor assembly and method of manufacturing the semiconductor assembly. The semiconductor device includes a substrate, a conductive feature in the substrate, an isolation liner between the substrate and the conductive feature, and a main component in the substrate. The conductive feature includes first to third blocks. The first block has a uniform first critical dimension, wherein the main component is disposed around the first block. The second block has a uniform second critical dimension greater than the first critical dimension. The third block is interposed between the first block and the second block and has varying third critical dimensions.

Abstract: Systems for physical unclonable function (“PUF”) generation, PUF devices, and methods for manufacturing PUF devices. In one implementation, the system includes a plurality of PUF devices and an electronic controller. Each of the plurality of PUF devices include a first electrochemically-inactive electrode, a second electrochemically-inactive electrode, and a layer of silicon suboxide. The layer of silicon suboxide is positioned directly between the first electrochemically-inactive electrode and the second electrochemically-inactive electrode. The electronic controller is communicably coupled to the plurality of PUF devices. The electronic controller is configured to read binary values associated with the plurality of PUF devices.

Abstract: A semiconductor device includes a substrate having a first region and a second region, first active fins that extend in a first direction in the first region, second active fins that extend in the first direction in the second region, a first field insulating layer between the first active fins and that extend in a second direction, a second field insulating layer between the second active fins and extending in the second direction, a gate line that extends in the second direction on the second field insulating layer, the gate line linearly along with the first field insulating layer, a gate isolation layer between the first field insulating layer and the gate line, and gate spacers that extend in the second direction, the gate spacers in contact with both sidewalls of each of the first field insulating layer, the gate line, and the gate isolation layer.

Abstract: Routing layers, e.g., back-end of line (BEOL) routing layers, of a semiconductor device are disclosed. Unlike conventional routing layers, the proposed routing layers include mixed pitch track patterns. As such, routing layers with reduced resistance-capacitance (RC) and low routing cost may be achieved.

Abstract: An interlayer dielectric layer covers an electric fuse element. A resistance layer made of silicon metal is arranged on the interlayer dielectric layer and directly above the electric fuse element.

Abstract: A semiconductor die includes a barrier layer of type III-V semiconductor material, a channel layer of type III-V semiconductor material disposed below the barrier layer, the channel layer forming a heterojunction with the barrier layer such that a two-dimensional charge carrier gas is disposed in the channel layer near the heterojunction, and a capacitor monolithically formed in the semiconductor die, wherein a dielectric medium of the capacitor includes a first section of the barrier layer.

Abstract: A semiconductor package includes; a lower semiconductor chip mounted on a lower package substrate, an interposer on the lower package substrate and including an opening, connection terminals spaced apart from and at least partially surrounding the lower semiconductor chip and extending between the lower package substrate and the interposer, a first molding member including a first material and covering at least a portion of a top surface of the lower semiconductor chip and at least portions of edge surfaces of the lower semiconductor chip, wherein the first molding member includes a protrusion that extends upward from the opening to cover at least portions of a top surface of the interposer proximate to the opening, and a second molding member including a second material, at least partially surrounding the first molding member, and covering side surfaces of the first molding member and the connection terminals, wherein the first material has thermal conductivity greater than the second material.

Abstract: Embodiments provide a method for manufacturing a microelectronic arrangement. The method includes a step of providing a chip-film module with a semiconductor chip and a film substrate having arranged thereon the semiconductor chip, wherein the chip-film module includes at least one coupling element spaced apart from the semiconductor chip and electrically coupled to at least one terminal of the semiconductor chip. Furthermore, the method includes a step of embedding the chip-film module into a printed circuit board, wherein, in embedding the chip-film module into the printed circuit board, the at least one coupling element of the chip-film module is coupled vertically [e.g. in the vertical direction [e.g. in relation to the printed circuit board]] [e.g. perpendicular to a surface of the printed circuit board] to at least one coupling counter element of the printed circuit board.

Abstract: Various embodiments of SST dies and solid state lighting (“SSL”) devices with SST dies, assemblies, and methods of manufacturing are described herein. In one embodiment, a SST die includes a substrate material, a first semiconductor material and a second semiconductor material on the substrate material, an active region between the first semiconductor material and the second semiconductor material, and a support structure defined by the substrate material. In some embodiments, the support structure has an opening that is vertically aligned with the active region.

Abstract: Sacrificial pillars for a semiconductor device assembly, and associated methods and systems are disclosed. In one embodiment, a region of a semiconductor die may be identified to include sacrificial pillars that are not connected to bond pads of the semiconductor die, in addition to live conductive pillars connected to the bond pads. The region with the sacrificial pillars, when disposed in proximity to the live conductive pillars, may prevent an areal density of the live conductive pillars from experiencing an abrupt change that may result in intolerable variations in heights of the live conductive pillars. As such, the sacrificial pillars may improve a coplanarity of the live conductive pillars by reducing variations in the heights of the live conductive pillars. Thereafter, the sacrificial pillars may be removed from the semiconductor die.

Abstract: Provided is a semiconductor module, including: a semiconductor chip; a circuit board on which the semiconductor chip is mounted; a sealing resin including epoxy resin for sealing the semiconductor chip and the circuit board; and a reinforcing material, with a higher Young's modulus than the sealing resin, provided in close contact with the sealing resin above at least a part of the sealing resin. The semiconductor module includes a resin case for enclosing spaces for housing the semiconductor chip, wherein the sealing resin may be provided inside the resin case.

Abstract: A method for manufacturing a light emitting display device, includes preparing a substrate having an active area and edge areas around the active area, forming a first electrode in each of a plurality of subpixels in the active area, forming a first common layer configured to cover an entirety of the active area and to have a first process margin in the edge areas outside the active area, forming a conductivity improvement layer on the first common layer in the edge areas, forming a light emitting layer in each of the subpixels, forming a second common layer having a large size than a size of the active area, on the light emitting layer, and forming a second electrode having a second process margin in the edge areas to cover at least the first common layer, on the second common layer.

Abstract: A semiconductor component includes an insulative layer having a lowermost surface arranged on top of a bottom dielectric material. The semiconductor component further includes a first interconnect structure arranged in the bottom dielectric material such that an uppermost surface of the first interconnect structure is arranged at a first height relative to the lowermost surface of the insulative layer. The semiconductor component further includes a pillar connected to the first interconnect structure and extending through the insulative layer. The semiconductor component further includes a second interconnect structure arranged in the bottom dielectric material such that an uppermost surface of the second interconnect structure is arranged at a second height relative to the lowermost surface of the insulative layer. The second height is different than the first height.

Abstract: An object of the present disclosure is to provide a technique capable of relaxing the stress to be applied around the attachment hole of the resin case at the time of fixing the resin case accommodating the semiconductor element to the heat dissipation component with a bolt. A semiconductor device includes a base plate, a heat dissipation component, and a resin case. In a state where the resin case is disposed on the heat dissipation component via the base plate, the resin case is attached to the heat dissipation component with a bolt. The resin case has a recess portion, an attachment hole formed below the recess portion, and at least one groove formed between a wall portion on an inner peripheral side forming the recess portion and the attachment hole. One end of the at least one groove reaches an outer peripheral end of the resin case.

Abstract: Provided is a memory device, including: a substrate; a plurality of word lines, extending in a first direction, arranged in a second direction, disposed on the substrate; a dummy structure, adjacent to ends of the word lines, disposed on the substrate, wherein the dummy structure includes a main part that extends in the second direction; and a plurality of extension parts, extending in the first direction, connected to the main part, and interposed between the main part and the word lines.

Abstract: A semiconductor device includes a fin structure including a recess formed in an upper surface of the fin structure, an inner gate formed in the recess of the fin structure, and an outer gate formed outside and around the fin structure.

Abstract: The present disclosure relates to an integrated chip structure. The integrated chip structure includes a first source/drain region and a second source/drain region disposed within a substrate. A select gate is disposed over the substrate between the first source/drain region and the second source/drain region. A ferroelectric random-access memory (FeRAM) device is disposed over the substrate between the select gate and the first source/drain region. A first sidewall spacer, including one or more dielectric materials, is arranged laterally between the select gate and the FeRAM device. An inter-level dielectric (ILD) structure laterally surrounds the FeRAM device and the select gate and vertically overlies a top surface of the first sidewall spacer.

Abstract: A semiconductor device including a fin structure including a recess, a first gate formed in the recess of the fin structure, and a second gate formed outside the fin structure.