Abstract: A method for manufacturing a polysilicon thin film transistor (TFT) according to the present invention reduces the electric field near the drain junction by varying partially the thickness of a gate insulating layer through a post oxide process. A polysilicon layer is patterned to become an active layer and a chemical vapor deposition oxide film deposited. By thermal oxidation a thermal oxide film is formed under the chemical vapor deposition oxide film. A gate electrode made of polysilicon is formed on the gate insulating layer. Thermal oxidation is performed to make the end portions of the thermal oxide film thicker than the portion under the gate electrode of the thermal oxide film. With this process, the electric field near the drain junction region is reduced and thus the leakage currents of the TFT decrease. In addition, the method in this invention is very simple compared with the conventional methods of obtaining a LDD structure and on-current is not reduced.

Abstract: A thin film transistor includes: a) a thin film transistor layer comprising a source region, a channel region and a drain region; the thin film transistor layer further comprising a drain offset region positioned between the drain region and the channel region; b) the channel region being substantially polycrystalline and having a first average crystalline grain size; and c) the drain offset region being substantially polycrystalline and having a second average crystalline grain size, the second average crystalline grain size being larger than the first average crystalline grain size. A method for forming such a construction using polycrystalline materials, preferably polysilicon, and an amorphizing silicon implant with subsequent recrystallization is also disclosed.

Abstract: A thin-film transistor structure having a storage-capacitor-on-gate and a black matrix for manufacturing a liquid crystal display is disclosed. A metal layer is deposited and patterned as a black matrix on a glass substrate of the thin-film transistor plate. An insulating layer having a contact hole for contacting the black matrix is formed over the surface of the black matrix and the substrate. An inverted thin-film transistor having a metal gate on the bottom is then fabricated on top of the insulating layer. The thin-film transistor controls an ITO pixel electrode of the liquid crystal display. A gate line including the metal gate of the thin-film transistor is formed over and above a space between two adjacent black matrixes. The gate line is connected to one of the two black matrixes by the contact hole. The other black matrix serves as a light shield element of the ITO pixel electrode.

Abstract: Using a nickel element which is a metal element for promoting crystallized of silicon, an amorphous silicon film is crystallization into a crystalline silicon film, and then a thin film transistor (TFT) is produced by using the crystalline silicon film. That is, a solution containing nickel (for example nickel acetate solution) which promotes crystallization of silicon is applied in contact with a surface of an amorphous silicon through the spin coat method. Then the heating treatment is performed to crystallize the amorphous silicon film into the crystalline silicon film. In the state, nickel silicide components are removed using a solution containing hydrofluoric acid, hydrogen peroxide and water.

Abstract: Thin-film transistors each having a different characteristic are selectively formed on the same substrate. A silicon oxide film, an amorphous silicon film, a barrier film for preventing the diffusion of a nickel element and an oxide film containing a nickel element that promotes the crystallization of silicon are sequentially formed on a glass substrate. The oxide film containing the nickel element is patterned and subjected to a heat treatment, to thereby crystallize the amorphous silicon film under the oxide film whereas the amorphous silicon film from which the oxide film has been removed remains as it is. After the heat treatment has been conducted, a laser light is irradiated on those films. On the silicon film which has been crystallized by heating, a laser light is irradiated in a state where even a necessary energy density is attenuated after the laser light transmits the oxide film, thereby promoting the crystalline property.

Abstract: A method for growing a single crystal III-V compound semiconductor layer, in which grown by vapor deposition on a first single crystal III-V compound semiconductor layer including at least Ga and N is a second single crystal III-V compound semiconductor layer different from the first layer and including at least Ga and N, comprises the steps of: growing a buffer layer other than single crystal and having substantially the same composition as that of the second layer by vapor deposition on the first layer; and growing the second layer on the buffer layer. A method for growing a single crystal AlGaN layer on a single crystal GaN layer by vapor deposition, comprises the steps of: growing a buffer layer of a III-V compound semiconductor including at least Ga and N on the single crystal GaN layer by vapor deposition; and growing the single crystal AlGaN layer on the buffer layer by vapor deposition.

Abstract: A wiring formed on a substrate is oxidized and the oxide is used as a mask for forming source and drain impurity regions of a transistor, or as a material for insulating wirings from each other, or as a dielectric of a capacitor. Thickness of the oxide is determined depending on purpose of the oxide.In a transistor adapted to be used in an active-matrix liquid-crystal display, the channel length, or the distance between the source region and the drain region, is made larger than the length of the gate electrode taken in the longitudinal direction of the channel. Offset regions are formed in the channel region on the sides of the source and drain regions. No or very weak electric field is applied to these offset regions from the gate electrode.

Abstract: A resist mask is formed on an electrode mainly made of aluminum. An anodic oxide film is formed on the electrode excluding the masked region by performing anodization in an electrolyte. A contact hole can easily be formed in the masked region because the anodic oxide film is not formed there. By removing a portion of the gate electrode which corresponds to an opening in forming a contact electrode, the gate electrode can be divided at the same time as the contact electrode is formed.

Abstract: A nitrogen-group III compound semiconductor satisfying the formula Al.sub.x Ga.sub.y In.sub.1-x-y N, inclusive of x=0, y=0 and x=y=0, and a method for producing the same comprising the steps of forming a zinc oxide (ZnO) intermediate layer on a sapphire substrate, forming a nitrogen-group III semiconductor layer satisfying the formula Al.sub.x Ga.sub.y In.sub.1-x-y N, inclusive of x=0, y=0 and x=y=0 on the intermediate ZnO layer, and separating the intermediate ZnO layer by wet etching with an etching liquid only for the ZnO layer.

Abstract: This circuit comprises an insulating substrate covered on at least part of its surface by a fine conducting layer (7) whose geometrical form corresponds to the layout chosen for the circuit; the said conducting layer having one or more very fine grooves (9) with a depth of more than 1 .mu.

Abstract: A method for counteracting increases in resistivity encountered when Indium Oxide resistive layers are subjected to high temperature annealing steps during semiconductor device fabrication. The method utilizes a recovery annealing step which returns the Indium Oxide layer to its original resistivity after a high temperature annealing step has caused the resistivity to increase. The recovery anneal comprises heating the resistive layer to a temperature between 100.degree. C. and 300.degree. C. for a period of time that depends on the annealing temperature. The recovery is observed even when the Indium Oxide layer is sealed under a dielectric layer.

Abstract: Methods of forming thin-film transistors include the steps of forming an amorphous silicon (a-Si) layer of predetermined conductivity type on a face of an electrically insulating substrate and then forming a first insulating layer on the amorphous silicon layer. The first insulating layer and amorphous silicon layer are then patterned to define spaced amorphous source and drain regions having exposed sidewalls. An amorphous silicon channel region is then deposited in the space between the source and drain regions and in contact with the sidewalls thereof. An annealing step is then performed to convert the amorphous source, drain and channel regions to polycrystalline silicon, prior to the step of forming an insulated gate electrode on the channel region.

Abstract: A method for forming a ferroelectric material film, more particularly a lead zirconate titanate (PZT) film by the sol-gel method wherein a lowered oxidative sintering temperature may be adopted in preparing the ferroelectric material film with a perovskite crystalline structure, thereby reducing the risk of oxidation of metal electrodes and other circuits when the ferroelectric material film is employed as a dielectric in semiconductor devices, such as in a capacitor, for example. The method contemplates the preparation of a raw material solution containing an organometallic compound of a metallic element forming the ferroelectric material film, alkanolamine and/or stabilizer comprising a .beta.-diketone, with the concentration of the stabilizer being sufficient to provide a mole ratio to the total metal atoms of (stabilizer/total metal atoms)>3.

Abstract: A vertical PNP transistor and method for making it provide a transistor in a surface layer (12), which may be an epitaxial layer, of P- type conductivity at a surface of a substrate (11) of P+ type conductivity. An isolation region (14) of N- type conductivity in the P- surface layer (12) contains a collector region (25) of P- type conductivity. A base region (30) of N type conductivity is contained in the collector region (25), and an emitter region (40) of P+ type conductivity is contained in the base region (30). The base region (30) may be provided with a higher N type impurity concentration than a P type impurity concentration of the collector region (25). At least the collector region (25) and the base region (30) may be self aligned. The collector region (25) may be of thickness of about 2.2 .mu.m, the base region (30) of thickness of about 0.1 .mu.m, and the emitter region (40) of thickness of about 0.4 .mu.m.

Abstract: A method of fabricating a field effect thin film transistor is provided, in which, after a first amorphous semiconductor layer having a predetermined thickness is deposited on a gate insulating film, the first amorphous semiconductor layer is transformed to a micro-crystal semiconductor layer by exposing it to hydrogen plasma produced by hydrogen discharge and, then, a second amorphous semiconductor layer is deposited on the micro-crystal semiconductor layer. According to this method, it is possible to fabricate a high performance and high quality field effect thin film transistor through a simplified step of forming the micro-crystal semiconductor which becomes a channel region thereof.

Abstract: In a method of forming a II-VI compound semiconductor thin film on an InP substrate, a layer of III-V compound semiconductor mixed crystal is first formed on the InP substrate. The desorption rate of a group V element constituting the III-V compound semiconductor mixed crystal at a decomposition temperature of a native oxide layer formed on a surface of the III-V compound semiconductor mixed crystal layer is lower than a desorption rate of P of the InP substrate at a decomposition temperature of a native oxide layer formed on a surface of the InP substrate. A II-VI compound semiconductor thin film layer is formed on the first III-V compound semiconductor mixed crystal layer.

Abstract: A process for fabricating an electronic circuit by oxidizing the surroundings of a metallic interconnection such as of aluminum, tantalum, and titanium, wherein anodic oxidation is effected at a temperature not higher than room temperature, preferably, at 10.degree. C. or lower, and more preferably, at 0.degree. C. or lower. The surface oxidation rate of a metallic interconnection can be maintained constant to provide a surface free of irregularities.

Abstract: A substrate has defined therein one or more active regions. A layer of polysilicon is deposited and patterned to form gates for various CMOS devices. A masking layer is then deposited and selectively etched to leave exposed portions of the substrate. Dopants of a first conductivity type are implanted into the exposed portions of the substrate to form one or more well regions of the first conductivity type. Using this masking layer and the polysilicon gates left exposed thereby as a mask, dopants of a second conductivity type are then implanted into the substrate to form source and drain regions of the second conductivity type in the well regions of the first conductivity type. The masking layer is then removed. In this manner, source and drain regions may be formed using the same masking layer used to define the well within which the source and drain regions lie, thereby reducing both time and expense in the fabrication of CMOS devices.

Abstract: A process for reducing halogen concentration in a material layer (56) includes the deposition of a dielectric layer (58) overlying the material layer (56). An annealing process is carried out to diffuse halogen atoms from the material layer (56) into the overlying dielectric layer (58). Once the diffusion process is complete, the dielectric layer (58) is removed.

Abstract: A method of manufacturing a raised source/drain MOSFET by depositing amorphous silicon on the partially formed MOSFET having the gate and gate oxide spacers formed, ion implanting to form the appropriate source/drain junctions, annealing wherein epitaxial growth takes place in regions where the amorphous silicon is over silicon, and etching the remaining amorphous silicon. A layer of refractory metal is deposited and a second anneal converts the refractory metal overlaying silicon to silicide.