Abstract: A method of manufacturing a semiconductor device, comprises the steps of: forming a first insulating film on a first substrate; forming a second insulating film on the first insulating film; forming an amorphous silicon film on the second insulating film; holding a metal element that promotes the crystallization of silicon in contact with a surface of the amorphous silicon film; crystallizing the amorphous silicon film through a heat treatment to obtain a crystalline silicon film; forming a thin-film transistor using the crystalline silicon film; forming a sealing layer that seals the thin-film transistor; bonding a second substrate having a translucent property to the sealing layer; and removing the first insulating film to peel off the first substrate.

Abstract: A process for formation of thin film transistors (TFTs) on plastic substrates replaces standard thin film transistor fabrication techniques, and uses sufficiently lower processing temperatures so that inexpensive plastic substrates may be used in place of standard glass, quartz, and silicon wafer-based substrates. The process relies on techniques for depositing semiconductors, dielectrics, and metals at low temperatures; crystallizing and doping semiconductor layers in the TFT with a pulsed energy source; and creating top-gate self-aligned as well as back-gate TFT structures. The process enables the fabrication of amorphous and polycrystalline channel silicon TFTs at temperatures sufficiently low to prevent damage to plastic substrates. The process has use in large area low cost electronics, such as flat panel displays and portable electronics.

Abstract: A method for crystallizing a portion of a semiconductor thin film while forming a semiconductor device comprises providing a transparent substrate supporting a metallic gate electrode and an amorphous semiconductor thin film which are separated from each other by a gate insulating film, heating the gate electrode by subjecting it to light rays, and applying a laser beam to the amorphous semiconductor thin film so that the portion of the semiconductor thin film adjacent the metallic gate electrode is heated by both the laser beam and the heat of the gate electrode to cause a crystallization of a portion of the amorphous thin film and then processing the remaining amorphous portions of the thin film to form the transistor structure.

Abstract: The formation of contact holes and a capacitor is performed in a semiconductor integrated circuit such as an active matrix circuit. An interlayer insulator having a multilayer (a lower layer is silicon oxide; an upper layer is silicon nitride) each having different dry etching characteristic is formed. Using a first mask, the silicon nitride corresponding to the upper layer in the interlayer insulator is etched by dry etching. This etching is completed by using the silicon oxide corresponding to the lower layer as an etching stopper. A pattern is formed using a second mask to form selectively the silicon oxide corresponding to the lower layer. Thus a first portion that the silicon oxide and the silicon nitride are etched and a second portion that only silicon nitride is etched are obtained. The first portion is used as a contact hole. A capacitor is formed in the second portion.

Abstract: The present invention relates to forming a narrow gate MOSFET having a local ion implantation to reduce the junction capacitance. A polysilicon layer is formed over a semiconductor substrate. An opening is formed in the polysilicon layer by using patterning and etching. Subsequently, a thermal oxidation is performed to oxidize the polysilicon layer into a polysilicon-oxide layer that is expanded in volume relative to the polysilicon layer thereby narrowing said opening. Then an ion implantation is performed by using said polysilicon-oxide layer as a mask.

Abstract: A composite-layer semiconductor device includes a gate above a host substrate, an n++ contact layer above the gate, and source and drain ohmic contacts applied to the n++ contact layer. The source and drain ohmic contacts define a central gate location which is recessed through the n++ contact layer toward the gate. The source and drain ohmic contacts create a barrier to chemical etching so that a current path below the central gate location can be incrementally recessed in repeated steps to precisely tailor the operating mode of the device for depletion or enhancement applications. The composite-layer semiconductor device is fabricated by depositing a gate on an n++ contact layer above a semi-insulating substrate. The semi-insulating substrate and gate are flipped onto an epoxy layer on the host substrate so that the gate is secured to the epoxy layer and the semi-insulating substrate presents an exposed backside. A portion of the exposed backside is removed.

Abstract: In a field effect type device having a thin film-like active layer, there is provided a thin film-like semiconductor device including a top side gate electrode on the active layer and a bottom side gate electrode connected to a static potential, the bottom side gate electrode being provided between the active layer and a substrate. The bottom side gate electrode may be electrically connected to only one of a source and a drain of the field effect type device. Also, the production methods therefor are disclosed.

Abstract: A radiation-hard, low-power semiconductor device of the complementary metal-oxide semiconductor (CMOS) type which is fabricated with a sub-micron feature size on a silicon-on-insulator (SOI) substrate (12). The SOI substrate may be of several different types. The sub-micron CMOS SOI device has both a fabrication and structural complexity favorably comparable to conventional CMOS devices which are not radiation-hard. A method for fabricating the device is disclosed.

Abstract: A process which prevents abnormal WSi.sub.x oxidation during subsequent LPCVD insulator deposition and gate sidewall oxidation, uses an in-situ deposition of a thin amorphous silicon layer on top of the tungsten silicide as well as the deposition of an amorphous spacer after gate stack patterning, respectively.

Abstract: The method of the present invention introduces a method of forming conductively doped contacts on a supporting substrate in a semiconductor device that minimizes the lateral out-diffusion of the conductive dopants and also provides for a low resistive contact by the steps of: preparing a conductive area to accept contact formation; forming a phosphorus insitu doped polysilicon layer over the conductive area; forming an arsenic insitu doped polysilicon layer over the phosphorus insitu doped polysilicon layer, wherein the two insitu doped polysilicon layers are deposited one after another in separate deposition steps; and annealing the layers at a temperature range of approximately 900.degree.-1100.degree. C. thereby, resulting in sufficient thermal treatment to allow phosphorus atoms to break up a first interfacial silicon dioxide layer formed between the conductive area and the phosphorus insitu doped polysilicon layer.

Abstract: A semiconductor processing method of providing a polysilicon layer atop a semiconductor wafer comprises the following sequential steps: a) depositing a first layer of arsenic atop a semiconductor wafer; b) depositing a second layer of silicon over the arsenic layer, the second layer having an outer surface; c) first annealing the wafer at a temperature of at least about 600.degree. C. for a time period sufficient to impart growth of polycrystalline silicon grains in the second layer and providing a predominately polysilicon second layer, the first annealing step imparting diffusion of arsenic within the second layer to promote growth of large polysilicon grains; and d) with the second layer outer surface being outwardly exposed, second annealing the wafer at a temperature effectively higher than the first annealing temperature for a time period sufficient to outgas arsenic from the polysilicon layer.

Abstract: A semiconductor on insulator structure (50) includes a silicon layer (30) formed on an insulating substrate (20). The silicon layer (30) is partitioned into two sections (32, 34) which are electrically isolated from each other. The thickness of the silicon layer (30) in a first section (32) of the silicon layer (30) is adjusted independently from the thickness of the silicon layer (30) in a second section (34) of the silicon layer (30). Independently adjusting the thickness of the silicon layer (30) allows optimizing the performance of semiconductor devices (60, 80) fabricated in the first and second sections (32, 34) of the semiconductor on insulator structure (50).

Abstract: An improved process for forming titanium silicide layers on semiconductor device silicon regions which have native oxide thereon utilizes a reactively sputter deposited layer of TiH.sub.x.ltoreq.2 followed by a rapid thermal anneal in a nitrogen bearing gas. This process results in lowered silicidation activation energy and lower anneal temperature requirements. Production throughput is improved with respect to prior art methods of removing the native oxide or minimizing its negative effect on silicide formation. The same process produces a titanium nitride/titanium silicide bilayer on silicon, and a titanium nitride/titanium bilayer on silicon dioxide. The thickness of the titanium nitride layer over silicon dioxide is enhanced by the use of TiH.sub.x.ltoreq.2 in place of Ti layers used in prior art, thus improving the utility of the titanium nitride as a diffusion barrier layer.

Abstract: A method of forming a spacer (41) around a gate electrode (32) includes sequentially disposing a first layer (48), a second layer (36), and a third layer (37) of dielectric over a semiconductor substrate (31) and over the gate electrode (32) and, thereafter, sequentially etching the third (37), second (36), and first (48) layers. The third layer (37) is etched with a first etchant to define a width (51) for the spacer (41). The first etchant selectively etches the third layer (37) versus the second layer (36). Etching the third layer (37) does not expose the first layer (48) located beneath the second layer (36). A second etchant, which is different from the first etchant, is used to selectively etch the second layer (36) versus the first layer (48). Etching the second layer (36) does not expose the semiconductor substrate (31) located beneath the first layer (48).

Abstract: A cold electron emitting device has an emitter base portion, an emitter projection portion and a source region, each of which is an n-type semiconductor, formed on a p-type silicon substrate. A metal film which serves as an extraction electrode and a gate electrode of FET is formed via an insulating layer on the region of the substrate which includes the peripheral regions of the emitter base portion and source region. This cold electron emitting device can be manufactured as follows. First, a conical emitter having an emitter projection portion and emitter base portion and a source region are formed on a p-type semiconductor substrate. Next, an insulating layer and a metal film, which becomes an extraction electrode and a gate electrode of FET, is formed on the substrate which includes peripheral regions of the emitter base portion and source region. Then, an n-type impurity is doped in the emitter and the source region to form an n-type emitter and an n-type source region.

Abstract: A process of Pb/Sn evaporation eliminates haloes in the manufacture of solder bump interconnects. This robust process of forms solder bump interconnects and reduces critical molebdnum mask sensitivity. Vacuum evaporation through which Pb/Sn C4 pads are deposited is performed by maintaining parallel temperature gradients between the molybdenum mask and silicon wafer, thus resulting in elimination of connecting haloes and yield losses.

Abstract: A method of manufacturing a large-area electronic device such as a flat panel display, which method includes subjecting a semiconductor film on a polymer substrate to an energy beam treatment, e.g., for crystal growth or to anneal an ion implant, and masking the substrate prior to treatment to prevent exposure to the energy beam, wherein the adhesion of the film and other layers on the substrate is improved by first heating the substrate to pre-shrink it, and then depositing the layers on the pre-shrunk substrate at a lower temperature than the heating temperature.

Abstract: A gate insulating film covering active layers of a insulated gate field effect semiconductor device utilizing a thin film silicon semiconductor comprises a thin film having the chemical formula SiO.sub.x N.sub.y. By making the concentration of N (nitrogen) high at the interface between the gate insulating film and the gate electrodes, it is possible to prevent the material composing the gate electrodes from being diffused in the gate insulating film. By making the concentration of N (nitrogen) high at the interface between the gate insulating film and the active layers, it is possible to prevent hydrogen ions and other ions from diffusing into the gate insulating film from the active layer.

Abstract: The specification describes techniques for cleaving crystal bodies, e.g. semiconductor laser bars, using thermostatic cleaving tools. Use of such tools allows the cleaving process to occur in an ultra high vacuum chamber without the use of mechanical devices activated from the exterior of the chamber. Cleaving occurs automatically and controllably by locally heating the cleaving tools, thereby deflecting the thermostatic element against the laser bar and causing fracture.

Abstract: A method for fabricating amorphous silicon thin film transistors (TFTs) with a polycrystalline silicon surface channel region for enhanced forward current drive. The method is particularly adapted for producing top-gate silicon TFTs which have the advantages of both amorphous and polycrystalline silicon TFTs, but without problem of leakage current of polycrystalline silicon TFTs. This is accomplished by selectively crystallizing a selected region of the amorphous silicon, using a pulsed excimer laser, to create a thin polycrystalline silicon layer at the silicon/gate-insulator surface. The thus created polysilicon layer has an increased mobility compared to the amorphous silicon during forward device operation so that increased drive currents are achieved. In reverse operation the polysilicon layer is relatively thin compared to the amorphous silicon, so that the transistor exhibits the low leakage currents inherent to amorphous silicon.