Abstract: A method of low temperature and rapid silicon crystallization or rapid transformation of amorphous silicon to high quality polysilicon over a large area is disclosed using a pulsed rapid thermal annealing (PRTA) method and a metal seed layer. The PRTA method forms polysilicon thin film transistors (TFTs) with a high throughput, on low temperature and large area glass substrates. The PRTA method includes the steps of forming over a glass layer a tri-layer structure having a layer of amorphous silicon sandwiched between bottom and top dielectric layers; selectively etching the top dielectric layer to expose portions of the amorphous silicon layer; forming a metal seed layer over the exposed portions of the amorphous silicon layer; and pulsed rapid thermal annealing using successive pulses separated by rest periods to transform the amorphous silicon layer to a polysilicon layer. In an alternate PRTA method, instead of forming the tri-layer structure, a bi-layer structure is formded over the glass layer.

Abstract: A method of manufacturing a device whereby a layer structure with semiconductor elements and conductor tracks is formed on a first side of a semiconductor wafer which is provided with a layer of semiconductor material disposed on an insulating layer. Then the semiconductor wafer is fastened with said first side to a support wafer by means of a glue layer, the support wafer being provided with a metallization. Material is then removed from the semiconductor wafer from the other, second side thereof until the insulating layer is exposed. Contact windows are provided in the insulating layer from the first side of the semiconductor wafer before the latter is refastened on the support wafer. These windows are filled with a material which can be removed selectively relative to the insulating layer. The contact windows are opened from the second side of the semiconductor wafer after the latter has been fastened on the support wafer and after the insulating layer has been exposed.

Abstract: A crystalline silicon thin film transistor having an LDD (lightly doped drain) structure and a process for fabricating the same, which comprises establishing an LDD by forming a gate insulating film and a gate electrode on an island-like semiconductor region and implanting thereafter impurities in a self-aligned manner to establish an LDD, anodically oxidizing the gate electrode and introducing impurities to form source and drain regions, partially or wholly removing the anodic oxide from the surface of the island-like semiconductor region to expose the LDD region, and irradiating a laser beam or an intense light having an intensity equivalent to that of the laser beam to activate the impurity region inclusive of the LDD.

Abstract: A method for forming a polycrystalline semiconductor thin film according to the present invention includes the steps of: forming a semiconductor thin film partially containing microcrystals serving as crystal nuclei for polycrystallization on an insulating substrate; and polycrystallizing the semiconductor thin film by laser annealing.

Abstract: A thin film transistor and a fabricating method for a thin film transistor is disclosed which may be suitable for memory cells of a static random access memory (SRAM) or other devices. A thin film transistor according to this invention may include an insulation substrate, a gate electrode formed to have a negative slope at one side thereof on the insulation substrate, an insulation film side wall formed at the other side of the gate electrode, a gate insulation film formed on the insulation substrate, gate electrode and side wall, a semiconductor layer formed on the gate insulation film, impurity diffusion regions selectively formed within the semiconductor layer over the gate electrode, the side wall and the insulation substrate on the other side of the gate electrode, and a channel region formed within the semiconductor layer at the side of the gate electrode having the negative slope.

Abstract: A method of fabricating a semiconductor device comprises the steps of preparing a transparent support substrate, forming a first gate electrode comprising semiconductor single crystal silicon by epitaxial growth on the transparent support substrate, forming an insulating film over the first gate electrode, forming a through-hole in the insulating film to expose a portion of the first gate electrode, laterally and epitaxially growing a semiconductor single crystal silicon thin film over the transparent substrate by epitaxial growth in the through-hole of the insulating film, forming a transistor element having a channel region formed in the semiconductor single crystal silicon thin film, and forming a second gate electrode over and electrically insulated from the channel region.

Abstract: It is intended to provide a technique of separately forming thin-film transistors disposed in a peripheral circuit area and those disposed in a pixel area in accordance with characteristics required therefor in a manufacturing process of semiconductor devices to constitute a liquid crystal display device. In an annealing step by laser light illumination, laser light is selectively applied to a semiconductor thin-film by partially masking it. For example, to illuminate the peripheral circuit area and the pixel area with laser light under different conditions in manufacture of an active matrix liquid crystal display device, laser light is applied at necessary illumination energy densities by using a mask. In this manner, a crystalline silicon film having a necessary degree of crystallinity in a selective manner can be obtained.

Abstract: A method for fabricating a silicon-germanium thin film field effect transistor (TFT) with a high carrier mobility and a high on/off ratio. An amorphous silicon layer, an amorphous germanium layer and a gate insulating film are successively layered on an insulating substrate on which a pair of source and drain electrodes are formed. Next, the amorphous silicon layer and the amorphous germanium layer are converted into polycrystalline layers by thermal annealing at a temperature higher than 600.degree. C. or laser annealing. Then, a gate electrode is formed on the gate insulating film.

Abstract: A semiconductor material and a method for forming the same, said semiconductor material having produced by a process comprising melting a noncrystal semiconductor film containing therein carbon, nitrogen, and oxygen each at a concentration of 5.times.10.sup.19 atoms.cm.sup.-3 or lower, preferably 1.times.10.sup.19 atoms.cm.sup.-3 or lower, by irradiating a laser beam or a high intensity light equivalent to a laser beam to said noncrystal semiconductor film, and then recrystallizing the thus molten amorphous silicon film. The present invention provides thin film semiconductors having high mobility at an excellent reproducibility, said semiconductor materials being useful for fabricating thin film semiconductor devices such as thin film transistors improved in device characteristics.

Abstract: Each of a pair of complementary insulated-gate field-effect transistors is manufactured in an asymmetric lightly doped drain structure that enables the source characteristics to be decoupled from the drain characteristics. Each transistor has a multi-part channel formed with an output portion, which adjoins the drain zone, and a more heavily doped input portion, which adjoins the source zone. The drain zone of each transistor contains a main portion and a more lightly doped extension that meets the output channel portion. The drain extension of each transistor typically extends at least as far below the upper semiconductor surface as the main drain portion so as to help reduce hot-carrier effects. The input channel portion of each transistor is situated in a threshold body zone whose doping determines the threshold voltage. Importantly, the provision of lightly doped source extensions is avoided so that improving the drain characteristics does not harm the source characteristics, and vice versa.

Abstract: A semiconductor device (83)including a transistor (85) with a nonuniformly doped channel region can be formed with a relatively simple process without having to use high dose implants or additional heat cycles. In one embodiment, a polysilicon layer (14) and silicon nitride layer (16) are patterned at the minimum resolution limit. The polysilicon layer is then isotropically etched to form a winged gate structure (32). A selective channel implant step is performed where ions are implanted through at least one of the nitride wings of the winged gate structure (32) but are not implanted through the polysilicon layer (14). Another polysilicon layer (64)is conformally deposited and etched such that the polysilicon (74) does not extend beyond the edges of the nitride wings.

Abstract: A semiconductor fabrication method is provided for forming transistors upon a semiconductor substrate wherein the semiconductor substrate has first, second and third substrate regions. A single mask layer is formed over the semiconductor substrate. The single mask layer has a first mask portion covering the first substrate region, a second mask portion exposing the second substrate region, and a third mask portion partially covering the third substrate region. A first type impurity dopant is differentially introduced into the first, second and third substrate regions according to the single mask layer. First, second and third transistors are formed in the first, second and third substrate regions, respectively. The first and second transistors have differing conductivity types and the first and third transistors have the same conductivity type. The first and third transistors also have differing threshold voltages according to the differential introducing of the dopant.

Abstract: A method for the formation of active devices upon and within exposed surfaces of both sides of a silicon wafer is presented. A dual-sided silicon wafer is provided having a first surface and an opposed second surface prepared similarly to achieve surfaces suitable for fabricating semiconductor devices. The method advantageously integrates the ability to preform wafer processing operations on both exposed surfaces separately or simultaneously. Wafer processing operations are layering, patterning, doping, and heat treatment. The processing sequence is complete when a doped region and a patterened interconnect line electrically coupled thereto (i.e., minimal integrated circuits) are formed upon and within both surfaces of the dual-sided silicon wafer. A wafer handling system and processing station for dual-sided silicon wafers are described. In addition, a technique of applying a protective layer over one surface of a dual-sided silicon wafer is also described.

Abstract: A method for producing a substrate for forming a polysilicon thin film by forming an amorphous silicon film of a thickness not more than 200 .ANG., irradiating excimer laser light onto the amorphous silicon film to crystallize silicon particles contained in the amorphous silicon film; and irradiating the amorphous silicon film with hydrogen radicals to etch the amorphous silicon film.

Abstract: A semiconductor device and process for making the same are disclosed which incorporate a relatively large percentage of erbium dopant (1 to 5%) into a BST dielectric film 24 with small grain size (e.g. 10 nm to 50 nm). Dielectric film 24 is preferably disposed between electrodes 18 and 26 (which preferably have a Pt layer contacting the BST) to form a capacitive structure with a relatively high dielectric constant and relatively low leakage current. Apparently, properties of the thin film deposition and small grain size. including temperatures well below bulk BST sintering temperatures, allow the film to support markedly higher defect concentrations without erbium precipitation than are observed for bulk BST. For erbium doping levels generally between 1% and 3%, over an order of magnitude decrease in leakage current (compared to undoped BST) may be achieved for such films.

Abstract: A process for manufacturing a light valve device comprises forming a transparent insulating thin film layer on a surface of a semiconductor substrate, and forming a single crystal semiconductor thin film on a surface of the transparent insulating thin film layer. A portion of the single crystal semiconductor thin film is then removed and at least one pixel electrode is formed on the transparent insulating thin film layer at a region where the single crystal semiconductor thin film has been removed. A driving unit is then formed in the single crystal semiconductor thin film. Thereafter, a carrier substrate is laminated using an adhesive on the surface of the semiconductor substrate at a region corresponding to the pixel electrode and the driving unit. The semiconductor substrate is then removed to expose a surface of the transparent insulating thin film layer and through-holes and a metal film are formed on the exposed surface thereof.

Abstract: A thin film transistor matrix device is fabricated by forming a transparent conductor film and a metal film on an insulating substrate in this order. The metal film and the transparent conductor film are together patterned to form picture element electrodes, and drain bus lines or gate bus lines. Source electrodes and drain electrodes may also be formed from the transparent conductor film and metal film. A semiconductor layer, an insulating film and a conductor film may be formed on the entire surface in this order. In this case, the conductor film, the insulator film and the semiconductor layer are patterned to form an active layer from the semiconductor layer, gate insulating films from the insulating film, and gate electrodes and gate bus lines from the conductor film. By patterning the conductor film, the insulating film and the semiconductor layer, the metal film of the picture element electrodes and drain bus lines is exposed.

Abstract: A method of etching openings in a dielectric layer of a semiconductor device by utilizing a novel etchant gas system of sulfur hexafluoride/chlorine such that sloped sidewalls can be formed in the openings having a desired taper of between about 20.degree. and about 85.degree. for achieving improved step coverage and profile control of the TFT fabrication process.

Abstract: In a method for fabricating a ULSI MOSFET with SOI structure, an additional polysilicon layer is used to form polysilicon/metal compound metal contacts on source and drain regions and a gate so as to avoid leakage current and short channel effect problems.

Abstract: A semiconductor device comprises a semiconductor substrate of a first conductivity type with a first insulating layer formed on the semiconductor substrate and a thin film field effect transistor with a control gate containing a refractory metal silicide formed on the semiconductor substrate over the first insulating layer. A second insulating layer covers the control gate electrode. A semiconductor film is formed on the semiconductor substrate over the first and second insulating layers and having a first region of a second conductivity type opposite to the first conductivity type. A second region of the first conductivity type is formed in contact with a first end of the first region. A third region of the first conductivity type is formed in contact with a second end of the first region. The control gate electrode and a part of the first region are overlapped with each other over the second insulating layer.