Abstract: In accordance with an embodiment, a synchronous N pulse burst generator includes an input for an intermediate frequency trigger signal and a signal path extending from the input. The signal path includes a series of N AND gates and an OR gate. Each AND gate is arranged to receive two inputs from the signal path. The signal path introduces a time delay between the two inputs received by each AND gate. A second input of the two inputs is inverted. The signal path introduces the time delay between successive AND gates from the series of N AND gates. An OR gate receives outputs from the series of N AND gates and outputs an A/D clock signal.

Abstract: Circuits, methods, and apparatus that may compensate for an incompatibility between connection detection schemes used by different interface circuits for different connector receptacles. One example may provide an active pull-down that normally provides a pull-down resistor and provides an open circuit for a period of time following a disconnection of an interface from a cable.

Abstract: A voltage level translation circuit includes a first energy storage unit, a second energy storage unit, a first voltage level translation unit, and a second voltage level translation unit. The first voltage level translation unit is configured to translate a first communication interface transmitting pin voltage signal to realize a first communication between a first communication interface transmitting pin and a second communication interface receiving pin. The second voltage level translation unit is configured to translate a second communication interface transmitting pin voltage signal to realize a second communication between a second communication interface transmitting pin and a first communication interface receiving pin. A multiple interface communication system is also provided.

Abstract: A delay-locked loop includes multiple inverters coupled together, wherein the inverters receive an input clock signal and output a first clock signal and a second clock signal. The input clock signal passes through a first set of inverters having a first number of inverters to generate the first clock signal. The input clock signal also passes through a second set of inverters having a second number of inverters one inverter greater than the first number of inverters to generate the second clock signal. The delay-locked loop also includes a polarity matching block that receives the first clock signal and the second clock signal and changes polarity of one of the first clock signal and the second clock signal.

Abstract: A low capacitance n-channel analog switch circuit, a p-channel analog switch circuit, and a full CMOS transmission gate (T-gate) circuit are described. Resistive decoupling can be used to isolate the switch or T-gate from AC grounds, such as one or more switch control signal inputs or supply voltages. A semiconductor region that is separated from a body region of a pass field-effect transistor (FET) can be coupled to or driven to a voltage similar to the input voltage or other desired voltage to help reduce parasitic capacitance of the switch or T-gate. The switch or T-gate can have improved frequency bandwidth or frequency response. The switch can be useful in a programmable gain amplifier (PGA) or programmable gain instrumentation amplifier (PGIA) or other circuit in which excessive switch capacitance could degrade circuit performance.

Abstract: The present invention relates to a wireless power supply system including a remote device capable of both transmitting and receiving power wirelessly. The remote device includes a self-driven synchronous rectifier. The wireless power supply system may also include a wireless power supply configured to enter an OFF state in which no power, or substantially no power, is drawn, and to wake from the OFF state in response to receiving power from a remote device.

Abstract: Exemplary embodiments of the present disclosure are directed to a bootstrapping module and logic circuits utilizing the bootstrapping module to compensate for a weak high condition. The bootstrapping module can be implemented using transistors have a single channel type that is the same as the channel type of transistors utilized in the logic circuits such that a truly unipolar circuit can be realized while addressing the weak high problem of such unipolar circuits.

Abstract: Devices and methods for generating an internal reset signal are explained. A first circuit (11) generates a first reset signal (r1), and a second circuit (12) generates a second reset signal (r2). The first reset signal (r1) and the second reset signal (r2) are linked to form a reset signal (r) with which a further circuit part (14) can be reset.

Abstract: A delta-sigma modulator circuit comprising: an integrator circuit configured to produce an integrator output signal that represents an integration of an analog input signal, a comparator output signal and a periodic signal; a comparator circuit configured to produce the comparator output signal in response to a comparison of the integrator output signal with a first reference signal; and a periodic signal generation circuit configured to produce the periodic signal.

Abstract: An electrical power supply system has a fuel cell module and a battery. The fuel cell can be selectively connected to the battery system through a diode. The system preferably also has a current sensor and a controller adapted to close a contactor in a by-pass circuit around the diode after sensing a current flowing from the fuel cell through the diode. The system may also have a resistor and a contactor in another by-pass circuit around the diode. In a start-up method, a first contactor is closed to connect the fuel cell in parallel with the battery through the diode and one or more reactant pumps for the fuel cell are turned on. A current sensor is monitored for a signal indicating current flow through the diode. After a current is indicated, a by-pass circuit is provided around the diode.

Abstract: The amplitude voltage of a signal input to a level shifter can be increased and then output by the level shifter circuit. Specifically, the amplitude voltage of the signal input to the level shifter can be increased to be output. This decreases the amplitude voltage of a circuit (a shift register circuit, a decoder circuit, or the like) which outputs the signal input to the level shifter. Consequently, power consumption of the circuit can be reduced. Alternatively, a voltage applied to a transistor included in the circuit can be reduced. This can suppress degradation of the transistor or damage to the transistor.

Abstract: A circuit suitable for data backup of a logic circuit is provided. The circuit includes first to fourth nodes, a capacitor, first to third transistors, and first and second circuits. Data can be loaded and stored between the circuit and the logic circuit. The first node is electrically connected to a data output terminal of the logic circuit. The second node is electrically connected to a data input terminal of the logic circuit. The capacitor is electrically connected to the third node. The first transistor controls electrical continuity between the first node and the third node. The second transistor controls electrical continuity between the second node and the third node. The third transistor controls electrical continuity between the second node and the fourth node. The first and second circuits have functions of raising gate voltage of the first transistor and raising gate voltage of the second transistor, respectively.

Abstract: Described herein is an N type extended drain transistor formed from a semiconductor on insulator (SOI) wafer. The transistor has a buried P type region formed by the selective implantation of P type dopants in a semiconductor layer of the wafer at a location directly below a drift region of the transistor. The transistor also includes a source located in a P well region and a drain. The buried P type region is in electrical contact with the P well region. The N type drift region, the source, and the drain are also located in a portion of the semiconductor layer surrounded by dielectric isolation. A buried dielectric layer located below the portion of the semiconductor layer electrically isolates the portion of the semiconductor layer from a semiconductor substrate located below the buried dielectric layer.

Abstract: An LED driver design has a single controller used to drive multiple strings of LEDs. In one aspect there is dynamic threshold voltage setting so that the individual characteristics of the LED strings can be taken into account in the voltage control loop. In another aspect, excess energy is dissipated off-chip in a dedicated heat dissipater, and the routing of current to the heat dissipater is controlled dynamically such that a desired integrated circuit biasing remains stable.

Abstract: A device (442) for producing a dynamic reference signal (UREF) for a control circuit for a power semiconductor switch comprises a reference signal generator (442) for providing a dynamic reference signal (UREF), which has a stationary signal level after elapse of a predefined time following a switching process of the power semiconductor switch, a passive charging circuit (450) which is configured to increase a signal level of the dynamic reference signal in reaction to a switching of a control signal of the power semiconductor switch from an OFF state to ON state for at least one part of the predefined time above the stationary signal level, in order to produce the dynamic reference signal and an output (A) for tapping the dynamic reference signal (UREF).

Abstract: An electronic circuit is disclosed. The electronic circuit includes a GaN substrate, a first power supply node on the substrate, an output node, a signal node, and an output component on the substrate, where the output component is configured to generate a voltage at the output node based at least in part on a voltage at the signal node. The electronic circuit also includes a capacitor coupled to the signal node, where, the capacitor is configured to selectively cause the voltage at the signal node to be greater than the voltage of the first power supply node, such that the output component causes the voltage at the output node to be substantially equal to the voltage of the first power supply node.

Abstract: A current clamp circuit includes a current-source circuit, a current-sense circuit, and a feedback circuit. The current-sense circuit includes a transistor, a resistive network, and a multiplexer. The transistor outputs a sensed current signal having a current that is equal to a current of an output signal provided by the current-source circuit. The feedback circuit limits the current of the sensed current signal and the output signal below a threshold current. The multiplexer modifies a resistance of the resistive network based on a first control signal. The multiplexer circuit and the feedback circuit are programmed using the first control signal and a second control signal when the transistor operates in a linear region and in a saturation region, respectively, to accurately output the sensed current signal.

Abstract: A semiconductor device, method of manufacture of a semiconductor device, and electronic system are disclosed. For example, the semiconductor device includes at least one trench disposed in a semiconductor substrate of the semiconductor device, wherein the semiconductor substrate has a first conductivity type. The semiconductor device further includes a polysilicon depleted gate shield disposed in the at least one trench, wherein the polysilicon depleted gate shield has a second conductivity type. The semiconductor device also includes a drift region disposed in the semiconductor substrate adjacent to at least one sidewall of the at least one trench, wherein the drift region has the first conductivity type, and a polysilicon gate disposed over the depleted gate shield in the at least one trench.

Abstract: In one aspect of the teachings herein, a switching circuit for switching a power transistor is configured to control the slew rate of the switched load current in a manner that yields substantial independence from the load voltage, based on the use of a Miller-effect compensation capacitor and controllable source resistances for driving the gate or base of the power transistor. In a non-limiting example, a control circuit, such as a microcontroller, uses a set of bidirectional input/output ports to drive the transistor base or gate through a selectable combination of parallel resistors, so that the effective source resistance for transistor turn-on and turn-off is selectable by configuring different combinations of input/output settings for the set of bidirectional input/output ports. Controlling the source resistance in this manner allows the control circuit to set or otherwise control the slew rate of the load current.

Abstract: An embodiment includes an apparatus comprising: a non-planar fin having first, second, and third portions each having major and minor axes and each being monolithic with each other; wherein (a) the major axes of the first, second, and third portions are parallel with each other, (b) the major axes of the first and second portions are non-collinear with each other, (c) each of the first, second, and third portions include a node of a transistor selected from the group comprising source, drain, and channel, (e) the first, second, and third portions comprise at least one finFET. Other embodiments are described herein.