Abstract: A semiconductor device, method of manufacture of a semiconductor device, and electronic system are disclosed. For example, the semiconductor device includes at least one trench disposed in a semiconductor substrate of the semiconductor device, wherein the semiconductor substrate has a first conductivity type. The semiconductor device further includes a polysilicon depleted gate shield disposed in the at least one trench, wherein the polysilicon depleted gate shield has a second conductivity type. The semiconductor device also includes a drift region disposed in the semiconductor substrate adjacent to at least one sidewall of the at least one trench, wherein the drift region has the first conductivity type, and a polysilicon gate disposed over the depleted gate shield in the at least one trench.

Abstract: Circuits, apparatuses, and methods are disclosed for frequency division. In one such example circuit, a frequency divider is configured to alternate between providing a common frequency clock signal as an output clock signal through a first circuit responsive to a reference clock signal and providing a reduced frequency clock signal as the output clock signal through a second circuit responsive to the reference clock signal. The first and second circuits share a shared circuit through which the output clock signal is provided. An enable circuit is configured to cause the frequency divider to alternate between providing the common frequency clock signal as the output clock signal through the first circuit and the reduced frequency clock signal as the output clock signal through the second circuit.

Abstract: A delay signal generating apparatus has a digitally controlled delay line and a control circuit. The digitally controlled delay line has a coarse delay circuit and a fine delay circuit. The coarse delay circuit generates a plurality of coarse delay signals by applying a plurality of different coarse delay amounts to an input signal, respectively, wherein the different coarse delay amounts are set by a first control input. The fine delay circuit generates a fine delay signal having a fine delay amount with respect to the input signal by performing phase interpolation based on the coarse delay signals, wherein the fine delay amount is set by a second control input. The control circuit generates the first control input to the coarse delay circuit, and generates the second control input to the fine delay circuit, wherein the control circuit does not change the first control input unless one of the coarse delay signals has no contribution to the fine delay signal according to the second control input.

Abstract: The invention relates to a device and to a method for producing a signal having an adjustable pulse duty factor, in particular a pulse-width-modulated signal. For this purpose, the period duration of the pulse-width-modulated signal can be varied. Thus, the pulse duty factor of the pulse-width-modulated signal can be adapted very accurately to the desired pulse duty factor without great switching complexity by using a simple counter with a fixed clock frequency.

Abstract: The present invention provides a frequency synthesizer that is switchable at a high speed and includes a few unnecessary frequency components in an output frequency signal. In a frequency synthesizer 1, a DDS 2 operates based on a clock signal to generate a reference frequency signal with a predetermined reference frequency, and clock signal supply units 41 and 42 switch the clock signals that have different clock frequencies to supply to the DDS 2. When the clock signals are switched to operate the DDS 2, the storage unit 12 stores a combination of a clock frequency fclk, a reference frequency fc, and a dividing number N in association with an output frequency fVCO of the frequency synthesizer 1 such that a spurious frequency does not exist within a predetermined frequency range and a dividing number of a variable frequency divider 302 disposed on a PLL circuit 3 is minimum. Setting units 11 and 24 read setting items stored in the storage unit 12 to set respective units.

Abstract: A signal receiver may include the following elements: a first transmission gate connected to an signal input terminal and receiving a first reference voltage; a enable switch connected to a first power supply terminal and receiving a first enable signal; a p-channel transistor connected to the enable switch and the first transmission gate; a first protection switch connected to the p-channel transistor and receiving the first reference voltage; a second transmission gate connected to the signal input terminal and receiving a second reference voltage; an n-channel transistor connected to a second power supply terminal, an signal output terminal, and the second transmission gate; a second protection switch connected to the signal output terminal, the n-channel transistor, and the first protection switch and receiving the second reference voltage; and a pull-down transistor connected to the second power supply terminal, the n-channel transistor, and the output terminal and receiving a second enable signal.

Abstract: A transistor monolithically integrated in a semiconductor body includes a first sub-transistor and a second sub-transistor that both include a first and second load contacts and a control contact for controlling an electric current through a load path. The first load contact of the first sub-transistor is electrically connected to the first load contact of the second sub-transistor and the second load contact of the first sub-transistor is electrically connected to the second load contact of the second sub-transistor. A control circuit is configured to cause the first sub-transistor to switch from a first state to a second state at a first point of time and to cause the second sub-transistor to switch from the first state to the second state at a second point of time subsequent to the first point of time.

Abstract: A circuit architecture and process that provides for a dual-mode methodology for an RF integrated circuit (IC) switch circuit that allows switching between a direct mapping configuration and a fully decoded mapping configuration, and further provides for changing either mapping configuration after fabrication. A control word is selectively compared to a programmed map register value so that, in a first mode, only one bit position of a control word matches a decoded programmed map bit pattern, and in a second mode, all bits of a control word match a corresponding programmed map bit pattern. Because the map registers can be programmed at least once after IC fabrication, the exact mapping required for a particular application can be determined post fabrication. Further, the first mode of operation is often beneficial during testing because multiple RF signal paths can be turned on at the same time and thus tested in parallel.

Abstract: An inverter apparatus includes a first capacitor, a second capacitor, a first switch, a second switch, a third switch, a fourth switch, a first inductor and a second inductor. The first capacitor, the second capacitor, the first switch, the third switch and the first inductor form and have functions of a half bridge inverter. The first capacitor, the second capacitor, the second switch, the fourth switch and the second inductor form and have functions of a half bridge inverter. Therefore, the present invention obtains two kinds of voltages.

Abstract: Direct current electric grids are provided that allow independent power generation and consumption at the neighborhood level. In an embodiment power is uploaded and downloaded to each node via monitoring of node voltage and setting high vs low priority loads to optimize for maximum power usage. Embodiments allow a new paradigm wherein electrical supply is set by total available installed power generation and wherein all available power is used, via prioritization. New apparatuses and circuits are provided that provide higher efficiency by utilizing solar power generated at low light conditions and by minimizing the number of power alteration steps between power generator and power consuming device.

Abstract: An example method includes: receiving, by an antenna of a receiver, RF power transmission waves from a transmitter, the RF waves forming controlled constructive interference patterns and destructive interference patterns in proximity to the receiver. The method also includes: transmitting, by the receiver to the transmitter, information used to determine a power level and efficiency of power received by the receiver device. The information that is used to determine the power level and efficiency indicates to the transmitter that the receiver device is receiving power at less than a maximum available efficiency. The method further includes: instructing a user of the receiver to change the receiver's position based on a comparison of respective voltage level or power received in each respective position or orientation of the receiver until a level of efficiency that is no less than the maximum available efficiency is achieved for the efficiency of power received.

Abstract: An electrical switch circuit adapted to switch digital, high-speed signals with low power includes a plurality of input buffers each coupled to an input transmission line of a plurality of input transmission lines, wherein each input buffer utilizes a digital inverter; a plurality of output buffers each coupled to an output transmission line of a plurality of output transmission lines, wherein each output buffer utilizes a digital inverter; and a plurality of switches each coupled to an associated input transmission line and an associated output transmission line, wherein each of the input transmission line, the output transmission line, and the plurality of switches are in a single line configuration. For the low power, each of the input buffers, the output buffers, the input transmission lines, and the output transmission lines can be unterminated.

Abstract: A comparator includes a current mirror module, a comparison module and a buffering and outputting module. The current mirror module provides a bias current to the comparison module. The comparison module comprises a positive input end, a first negative input end and a second negative input end, the positive input end connects to an external terminal, the first negative input end and the second negative input end input a low threshold voltage and a high threshold voltage, respectively. The comparison module compares a voltage of the positive input end to the low threshold voltage and the high threshold voltage, and outputs a comparison result to the buffering and outputting module.

Abstract: A clock correction device performs skew adjustment and duty correction of an input clock concurrently or in parallel. The clock correction device includes a correction circuit that performs skew adjustment of an input clock by analog control using a skew adjustment signal based on a phase difference between an output clock and a reference clock, receives a duty control signal, and performs duty correction of the input clock by digital control, a skew detection circuit that receives inputs of the output clock and the reference clock and, when only the reference clock is in a predetermined state, outputs a detection signal that changes to the predetermined state, an integration circuit that integrates the detection signal and generates a first voltage signal, and a comparator that compares the first voltage signal and a first reference signal to thereby generate the skew adjustment signal.

Abstract: Apparatuses, methods and systems for monitoring vehicle parking occupancy are disclosed. One method includes intermittently receiving, by a wireless node, a wireless signal from a vehicle sensing device, wherein the vehicle sensing device transmits the wireless signal upon sensing a change in vehicle occupancy of an associated parking location, wherein the wireless signal includes a vehicle sensing indicator, wherein the vehicle sensing indicator indicates whether the vehicle sensing device senses vehicle occupancy of the associated parking location, measuring a signal quality of the intermittently received wireless signal over time, correlating the measured signal quality of the intermittently received wireless signal over time with the vehicle occupancy indictor, and identifying errors in the vehicle sensing indicator based on the correlating of the measured signal quality of the intermittently received wireless signal over time with the vehicle occupancy indictor.

Abstract: A high-gain, low power, electronic amplifier for amplification of a low magnitude voltage signal through a comparator-integrator amplification method for energy-aware applications is disclosed. The electronic amplifier comprises: a comparator arrangement with at least one comparator unit adapted to receive a first voltage signal to be amplified and a first feedback voltage signal, and to generate a first two-level voltage comparison signal; a integrator arrangement to receive the first two-level voltage comparison signal and generate a first amplifier output signal corresponding to an amplification of the voltage signal to be amplified; and a first feedback network to receive the first amplifier output signal and generate the first feedback voltage signal.

Abstract: Apparatuses and methods for level shifting in a semiconductor device are described. An example apparatus includes: a splitter circuit that operates on a first voltage potential to produce a first signal having a first polarity and a second signal having a second polarity that is substantially opposite to the first polarity; an one-shot pulse circuit that operates on the first voltage potential to produce a first one-shot pulse signal responsive to the first signal and a second one-shot pulse signal responsive to the second signal; and a logic circuit configured to operate on a second voltage potential to produce a third signal responsive to the first and second one-shot pulse signals, the second voltage potential being different from the first voltage potential.

Abstract: A track and hold circuit comprises an input buffer amplifier, a unit gain amplifier module, a sampling switch, a drive triode and a sampling capacitor. The input buffer amplifier receives an input signal. In a track phase, the sampling switch is electrically connected to an emitter electrode of the drive triode; the input signal charges the sampling capacitor after being buffered by the input buffer amplifier, amplified without distortion by the unit gain amplifier module and driven by the drive triode. In a hold phase, the sampling switch is electrically connected to a base electrode of the drive triode; the base voltage of the drive triode is pulled down until the drive triode is cut off; electrical charges on the sampling capacitor are thereby held, causing the signal to be held on the sampling capacitor.

Abstract: A low dropout voltage (LDO) regulator including: a coarse loop circuit configured to receive an input voltage, generate a coarse code and adjust a coarse current according to the coarse code; a digital controller configured to receive the coarse code and generate a fine loop control signal according to the coarse code; and a fine loop circuit configured to receive the input voltage and the fine loop control signal and adjust a fine current according to the input voltage and the fine loop control signal, wherein the coarse current and the fine current adjust a level of an output voltage.

Abstract: An apparatus includes a first AC (alternating current) coupling circuit configured to receive a first end of a differential signal and output a first coupled signal in accordance with a bias voltage; a second AC coupling circuit configured to receive a second end of the differential signal and output a second coupled signal in accordance with the bias voltage; a first complementary joint-control cascode pair configured to shunt the first end of the differential signal to a DC (direct current) node in accordance with a joint control by the first coupled signal and the second coupled signal; and a second complementary joint-control cascode pair configured to shunt the second end of the differential signal to the DC node in accordance with a joint control by the first coupled signal and the second coupled signal. A related method is also provided.