Abstract: A large-power insulated gate switching device (e.g., MOSFET) is used for driving relatively large surges of pulsed power through a load. The switching device has a relatively large gate capacitance which is difficult to quickly discharge. A gate charging and discharging circuit is provided having a bipolar junction transistor (BJT) configured to apply a charging voltage to charge the gate of the switching device where the BJT is configured to also discontinue the application of the charging voltage. An inductive circuit having an inductor is also provided.

Abstract: A wireless power transmission apparatus and a wireless power transmission method includes: activating a first wireless transmission unit having a first transmission scheme and deactivating a second transmission unit having a second transmission scheme; transmitting power by the first transmission scheme when a reception scheme of a wireless power reception apparatus is same as the first transmission scheme; deactivating the first wireless transmission unit and activating the second wireless transmission unit when the reception scheme is different from the first transmission scheme; and transmitting the power by the second transmission scheme when the reception scheme is same as the second transmission scheme. Interference between the first wireless transmission unit and the second wireless transmission unit can be prevented from occurring by selectively or sequentially activating the first wireless transmission unit and the second wireless transmission unit.

Abstract: An output stage circuit comprises: a power inverter, coupled to a signal terminal; and a dynamic bias circuit, wherein the dynamic bias circuit connects between a system voltage terminal and the power inverter. The dynamic bias circuit comprises at least one Zener diode, which is configured to maintain a voltage difference between a gate terminal and a source terminal of at least one transistor of the power inverter within a first absolute value; which is configured to maintain a voltage difference between the gate terminal and a drain terminal of the at least one transistor within a second absolute value; and configured to maintain a voltage difference between the drain terminal and the source terminal of the at least one transistor within the second absolute value.

Abstract: According to one embodiment, a synchronous semiconductor device is disclosed According to this embodiment, the synchronous semiconductor device includes a pulse width detection circuit to provide detection information responsive to a plurality of delay amounts being different from one another and at least one of a high pulse width and a low pulse width of a first clock signal. The detection information representing relationships in size between each of the plurality of delay amounts and the at least one of the high pulse width and the low pulse width of the first clock signal. A delay line control circuit coupled to the pulse width detection circuit and the delay line. The delay line control circuit configured to change a delay amount of the delay line by a step size determined responsive, at least in part, to the detection information.

Abstract: Switching circuitry for use in a digital-to-analog converter, the circuitry comprising: a common node; first and second output nodes; and a plurality of switches connected between the common node and the first and second output nodes and operable in each clock cycle of a series of clock cycles, based on input data, to conductively connect the common node to either the first or second output node along a given one of a plurality of paths, wherein the circuitry is arranged such that a data-controlled switch and a clock-controlled switch are provided in series along each said path from the common node to the first or second output node.

Abstract: A semiconductor device is provided which realizes speed-up and cost reduction. The semiconductor device has a high side gate driver including a depression type FET and an enhancement type FET, a low side gate driver including a depression type FET and an enhancement type FET, and a high side power FET and a low side power FET as field-effect transistors, in which the high side gate driver, the low side gate driver, the high side power FET and the low side power FET are integrated in the same chip.

Abstract: A method for a mobile device in a wireless power system includes transmitting a request to a server of the wireless power system for acquiring operation state information of a first wireless power spot in the wireless power system, wherein the request at least comprises a required power threshold; and receiving a response comprising the operation state information of the first wireless power spot, wherein the operation state information at least comprises a capacity and an availability of the first wireless power spot.

Abstract: A system for electrically coupling a first structure with a second structure in a vehicle is disclosed, and includes a control module receiving at least one of electrical power and data, a cable, and a reel. The cable has a variable length and is electrically coupled to the control module. The cable transmits at least one of electrical power and data from the first structure to the second structure. The reel is located at the first structure and defines an axis of rotation. The cable is windable around the reel, and the reel is rotatable about the axis of rotation to adjust the variable length of the cable. The variable length of the cable is a portion of the cable that extends between the first structure to the second structure that is not wound around the reel.

Abstract: A power-gate circuit includes a power-gate transistor operable to switch to decouple a first supply voltage from a second supply voltage during an idle mode, and to couple the first supply voltage to the second supply voltage during a full operational mode. Part of the charge stored at a gate terminal of the power-gate transistor, would have been otherwise flushed to ground while turning on the power-gate transistor, is routed to the rail of the second supply voltage of the logic block. Part of the charge on the rail of the second supply voltage is used to charge the gate terminal of the power-gate transistor to deactivate the power-gate transistor if the logic block goes to the idle mode. Energy is saved both ways because of the charge recycling and the ability to use the power gate circuit even in cases where the duration of the idle mode may be short.

Abstract: A CMOS transmission gate that is compensated for lost current to parasitic capacitance. Parasitic capacitance current is detected by an amplifier and fed back in-phase to the input of the CMOS transmission gate with the gain of the amplifier set to avoid circuit instability. In a first example a transconductance amplifier detects a voltage drop across a resistor in and RC network and the resulting current applied to the input of the transmission gate. A second example uses a current amplifier to detect gate current of the N-channel and P-channel transistors of the transmission gate, and an output current is fed back in phase to the input of the CMOS transmission gate.

Abstract: A method for providing control power for an electricity network in which at least one energy store connected to the electricity network supplies energy to the electricity network as required and/or takes up energy from the electricity network as required, the control power being delivered in dependence on a frequency deviation from a setpoint value of a network frequency, tolerance with respect to the amount of the control power to be provided being used to set a charging state of the energy store at a same time as providing control power by the energy store. A device for carrying out such a method includes a control system and an energy store, the device being connected or connectable to an electricity network, the control system being connected to the energy store and controlling control power given off and/or taken up by the energy store.

Abstract: An integrated circuit and a code generating method are described. The integrated circuit includes a plurality of field effect transistors, a plurality of sense-amplifiers, and a processing circuit. Each field effect transistor is configured to represent an address in a mapping table and includes a source, a drain, a channel and a gate. Each sense-amplifier is connected to the drain and configured to sense an electric current from the drain and identify a threshold voltage of the corresponding field effect transistor. The processing circuit is configured to categorize each of the threshold voltages identified by the corresponding sense-amplifiers into a first state and a second state and mark the state of each of the threshold voltages at the corresponding address in the mapping table.

Abstract: Disclosed is an electronic device including a resonator that generates an induced current by electromagnetic coupling. The resonator includes a first conductor, a plurality of second conductors, a one end of each of the second conductors being electrically coupled to a first point of the first conductor, and an other end of each of the second conductors being electrically coupled to a second point of the first conductor, and at least one impedance load connected with the second conductors in series or in parallel. Thus, the resonator may generate current through the first and second conductors.

Abstract: A nanosecond pulser may include a plurality of switch modules, a transformer, and an output. Each of the plurality of switch modules may include one or more solid state switches. The transformer may include a core, at least one primary winding wound around at least a portion of the core, each of the plurality of switch modules may be coupled with the primary windings, and a plurality of secondary windings wound at least partially around a portion of the core. The output may output electrical pulses having a peak voltage greater than about 1 kilovolt and having a pulse width of less than about 1000 nanoseconds. The output may output electrical pulses having a peak voltage greater than about 5 kilovolts, a peak power greater than about 100 kilowatts, a pulse width between 10 nanoseconds and 1000 nanoseconds, a rise time less than about 50 nanoseconds, or some combination thereof.

Abstract: According to one aspect, the invention relates to a proximity detector (10) of a motor vehicle device (Eq), the proximity detector (10) comprising:—a detection antenna (1) generating a detection signal when a user (U) is in the proximity of said device (Eq);—a printed circuit (2) processing the detection signal in order to command an action of said device (Eq);—and a conducting rod (3) for electrical connection of the detection antenna (1) to the printed circuit (2).

Abstract: A semiconductor integrated circuit device may include a target PMOS transistor, a target NMOS transistor, a first stress-applying circuit, a second stress-applying circuit, a third stress-applying circuit and a fourth stress-applying circuit. An inverter may include the target PMOS transistor and the NMOS transistor. The first stress-applying circuit may be configured to apply a first DC level to a gate of the target PMOS transistor. The second stress-applying circuit may be configured to apply a second DC level to a gate of the target NMOS transistor. The third stress-applying circuit may be configured to apply an AC voltage shape to the gate of the target NMOS transistor. The fourth stress-applying circuit may be configured to apply the AC voltage to a drain of the target NMOS transistor.

Abstract: GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Both the high side and the low side devices may have one or more integrated control, support and logic functions. Some devices employ electro-static discharge circuits and features formed within the GaN-based devices to improve the reliability and performance of the half bridge power conversion circuits.

Abstract: A load control device for controlling the amount of power delivered to an electrical load may include a rectifier circuit configured to receive a phase-control voltage and produce a rectified voltage. A power converter may be configured to receive the rectified voltage at an input and generate a bus voltage. An input capacitor may be coupled across the input of the power converter. The input capacitor may be adapted to charge when the magnitude of the phase control voltage is approximately zero volts. The power converter may be configured to operate in a boost mode, such that the magnitude of the bus voltage is greater than a peak magnitude of the input voltage. The power converter may be configured to operate in a buck mode to charge the input capacitor from the bus voltage when the magnitude of the phase-control voltage is approximately zero volts.

Abstract: A low dropout linear regulator circuit comprises a voltage reference source module (100), an error amplifier (200), a reference voltage determining module (300), a power transmission device (400) and a feedback module (500); wherein the voltage reference source module (100) provides a reference voltage for the error amplifier (200), the reference voltage determining module (300) controls an enablement of the error amplifier (200) according to whether the voltage reference source module (100) is completely started, the error amplifier (200) controls ON/OFF of the power transmission device (400) according to the reference voltage provided by the voltage reference source module (100) and a feedback voltage provided by the feedback module (500). A chip having the above low dropout linear regulator circuit and a electronic device having the above chip are provided.

Abstract: Exemplary embodiments are directed to wireless power transfer including generating an electromagnetic field at a resonant frequency of a transmit antenna to create a coupling-mode region within a near-field of the transmit antenna. A receive antenna placed within the coupling-mode region resonates at or near the resonant frequency. The receive antenna extracts energy from a coupling between the two antennas. Signaling from the receive antenna to the transmit antenna is performed by generating a first power consumption state for the receive antenna to signal a first receive signal state and generating a second power consumption state for the receive antenna to signal a second receive signal state. Signaling from the transmit antenna to the receive antenna is performed by enabling the resonant frequency on the transmit antenna to signal a first transmit signal state and disabling the resonant frequency on the transmit antenna to signal a second transmit signal state.