Abstract: Provided is a double-side polishing apparatus and a double-side polishing method which make it possible to terminate double-side polishing with timing allowing a work having been polished to have a target shape. A computing unit 13 performs a step of grouping the data of thicknesses measured using work thickness measuring devices 11 on a work basis; a step of extracting shape components of each work from the thickness data; a step of identifying a position of each of the shape components in the work radial direction; a step of computing a shape distribution of the work from the identified position ; a step of obtaining a shape index of the work from the computed shape distribution; and a step of determining timing of termination of the double-side polishing based on the obtained shape index, thus timing of termination of the double-side polishing is determined.

Abstract: A semiconductor package includes an interposer including first and second surfaces opposite to each other. The semiconductor package also includes a heat dissipation layer disposed on the first surface of the interposer and a first semiconductor die mounted on the first surface of the interposer. The semiconductor package additionally includes a stack of second semiconductor dies mounted on the second surface of the interposer. The semiconductor package further includes a thermally conductive connection part for transferring heat from the stack of the second semiconductor dies to the heat dissipation layer.

Abstract: Disclosed are a semiconductor package and a manufacturing method thereof. Semiconductor chips may be disposed on a package substrate with vent holes formed therethrough, and a molding layer including a lower molding portion connected to an upper molding portion may be formed. The package substrate may include a substrate body with a plurality of unit regions, ball lands disposed in the unit regions, and first and second dam patterns that cross the unit regions and extend into edge regions, which is outside of the unit regions.

Abstract: Embodiments relate to a die package featuring a sputtered metal shield to reduce Electro-Magnetic Interference (EMI). According to a particular embodiment, a die featuring a top surface exposed by surrounding Molded Underfill (MUF) material, is subjected to metal sputtering. The resulting sputtered metal shield is in direct physical and thermal contact with the die, and is in electrical contact with a substrate supporting the die (e.g., to provide shield grounding). Specific embodiments may be particularly suited to reducing the EMI of a package containing an electro-optic die, to between 3-15 dB. The conformal nature and small thickness of the sputtered metal shield desirably conserves space and reduces package footprint. Direct physical contact between the shield and the die surface exposed by the MUF, enhances thermal communication (e.g., reducing junction temperature). According to certain embodiments, the sputtered metal shield comprises a stainless steel liner, copper, and a stainless steel coating.

Abstract: A semiconductor package is disclosed. The semiconductor package may include a substrate, a first semiconductor chip on the substrate, an inner mold layer provided on the substrate to at least partially enclose the first semiconductor chip, an inner shielding layer provided on the substrate to at least partially enclose the inner mold layer, a second semiconductor chip stack on the inner shielding layer, an outer mold layer provided on the substrate to at least partially enclose the inner shielding layer and the second semiconductor chip stack, and an outer shielding layer at least partially enclosing the outer mold layer. Each of the inner and outer shielding layers may include a conductive material, and the inner shielding layer may be electrically connected to a ground pad of the substrate.

Abstract: A method and a system for planarizing a membrane is disclosed. In one aspect, the method includes providing a resilient membrane and planarizing the surface of the membrane with a conditioning tool. The planarized membrane may be used in chemical mechanical planarization of a wafer. The method further includes finishing the surface of a wafer with the planarized membrane.

Abstract: A conductive member module has a pair of conductive members formed in a plate shape and facing each other, and a sealing part. The conductive member module is produced by performing an accommodation step, a sealing step, and an extraction step. In the accommodation step, the two individual conductive members are sandwiched in the facing orientation thereof by outer support members abutting outer surfaces of the conductive members, and inner support members abutting inner surfaces of the conductive members. Outer recesses are formed in the outer surfaces by the outer support members, and inner recesses are formed in the inner surfaces by the inner support members. The outer recesses are deeper in the Z direction than the inner recesses.

Abstract: A capacitor includes an active layer, a gate insulation layer on the active layer, a gate electrode on the gate insulation layer, an interlayer insulating layer on the gate electrode, and a first electrode on the interlayer insulating layer and connected to the active layer through at least one contact hole.

Abstract: A method of producing a semiconductor device includes: forming, in a semiconductor substrate, a drift region of a first conductivity type, a body region of a second conductivity type above the drift region, and a source region of the first conductivity type separated from the drift region by the body region; forming rows of spicular-shaped field plate structures in the semiconductor substrate, the spicular-shaped field plate structures extending through the source region and the body region into the drift region; forming stripe-shaped gate structures in the semiconductor substrate and separating adjacent rows of the spicular-shaped field plate structures; and forming a current spread region of the first conductivity type below the body region in semiconductor mesas between adjacent ones of the spicular-shaped field plate structures and which are devoid of the stripe-shaped gate structures, the current spread region configured to increase channel current distribution in the semiconductor mesas.

Abstract: The present disclosure relates to a solid-state imaging device capable of further decreasing reflectivity, a method of manufacturing the same, and an electronic device. The solid-state imaging device includes a semiconductor substrate on which a photoelectric converting unit is formed for each of a plurality of pixels, and an antireflection structure provided on a light incident surface side from which light is incident on the semiconductor substrate in which a plurality of types of projections of different heights is formed. The antireflection structure is formed by performing processing of digging a light incident surface of the semiconductor substrate in a plurality of stages with different processing conditions. The antireflection structure is the structure in which a second projection lower than a first projection is formed between the first projections of predetermined height. The present technology may be applied to a CMOS image sensor, for example.

Abstract: A chip package includes a redistribution layer, at least one first semiconductor chip, an integrated fan-out package, and an insulating encapsulation. The at least one first semiconductor chip and the integrated fan-out package are electrically connected to the redistribution layer, wherein the at least one first semiconductor chip and the integrated fan-out package are located on a surface of the redistribution layer and electrically communicated to each other through the redistribution layer, and wherein the integrated fan-out package includes at least one second semiconductor chip. The insulating encapsulation encapsulates the at least one first semiconductor chip and the integrated fan-out package.

Abstract: An electronic package is provided, including at least an electronic element and at least an antenna structure disposed on a carrier structure. The antenna structure includes a base portion configured with an antenna body and a plurality of support portions disposed on the base portion. As such, the base portion is disposed over the carrier structure through the support portions and a plurality of open areas are formed between the base portion and the carrier structure to serve as an air gap, thereby effectively improving the performance gain and efficiency of the antenna body.

Abstract: The present disclosure is directed to a polishing head for polishing a wafer by a slurry. The polishing head includes a main body and at least two air modules. The main body has a cavity for accommodating the wafer, a main channel, and at least two sub-channels connected to the main channel. The at least two air modules are disposed at an outer surface of the main body. Each of the air modules is respectively connected to one of the sub-channels of the main body and configured to generate an air stream. When the polishing head rotates, the air stream forms an air curtain around the outer surface of the main body.

Abstract: Embodiments disclosed herein include electronic packages for PoINT architectures. Particularly, embodiments include electronic packages that include reinforcement substrates to minimize warpage. In an embodiment, an electronic package comprises, a reinforcement substrate, a plurality of through substrate vias through the reinforcement substrate, a dielectric substrate over the reinforcement substrate, a cavity into the dielectric substrate, and a component in the cavity.

Abstract: In a substrate polishing apparatus where a polishing liquid passes through inside a rotary joint, the rotary joint requires maintenance. There is provided a substrate polishing apparatus that includes: a polishing head for holding a substrate; a rotary table that has a surface to which a first opening portion is provided; a polishing liquid discharge mechanism disposed to the rotary table; and a controller configured to control at least the polishing liquid discharge mechanism. The polishing liquid discharge mechanism includes a first cylinder, a first piston, and a driving mechanism that drives the first piston. The first opening portion is communicated with a liquid holding space defined by the first cylinder and the first piston. The controller controls the driving of the first piston by the driving mechanism to increase and decrease a volume of the liquid holding space.

Abstract: Provided is a method of double-side polishing a wafer by which variations of the GBIR values of polished wafers between batches can be reduced. In the method of double-side polishing a wafer, a current batch includes measuring the center thickness of the wafer before polishing (S100); setting a target GBIR value within a predetermined range (S110); calculating a polishing time of the current batch based on Formula (1) (S120); and polishing both surfaces of the wafer for the calculated polishing time (S130). Polishing time of current batch=polishing time of previous batch+A1×(center thickness of wafer before polishing in previous batch?center thickness of wafer before polishing in current batch)+A2×(GBIR value of wafer after polishing in previous batch?target GBIR value)+A3??(1), where A1, A2, and A3 are predetermined coefficients.

Abstract: A module (101) is provided with a substrate including a principal surface (1u), a plurality of electronic components (41, 42, and 43) arranged on the principal surface (1u), a sealing resin (3) covering the principal surface (1u), a ground electrode arranged on the principal surface (1u), a conductive layer (6) covering the sealing resin (3), and a magnetic member (5). The conductive layer (6) is electrically connected to the ground electrode by a plurality of connecting conductors (62) arranged so as to penetrate the sealing resin (3), and the magnetic member (5) includes a magnetic member plate-shaped portion arranged so as to cover the sealing resin (3) and a magnetic member wall-shaped portion (52) arranged in a wall shape in the sealing resin (3). The magnetic member wall-shaped portion (52) is longer than each of the connecting conductors (62).

Abstract: A polishing method capable of terminating polishing of a substrate, such as a wafer, at a preset polishing time is disclosed. The polishing method includes: polishing a substrate by pressing the substrate against a polishing surface of a polishing pad, while regulating a temperature of the polishing surface by a heat exchanger; calculating a target polishing rate required for an actual polishing time to coincide with a target polishing time, the actual polishing time being a time duration from start of polishing the substrate until a film thickness of the substrate reaches a target thickness; determining a target temperature of the polishing surface that can achieve the target polishing rate; and during polishing of the substrate, changing a temperature of the polishing surface to the target temperature by the heat exchanger.

Abstract: Provided is a forming method of a redistribution structure including: forming a first redistribution layer and a first compensation circuit layer on a substrate, wherein the first compensation circuit layer surrounds the first redistribution layer, and the first compensation circuit layer and the first redistribution layer are electrically insulated from each other; forming a first dielectric layer on the first redistribution layer and the first compensation circuit layer; and forming a second redistribution layer and a second compensation circuit layer on the first dielectric layer, wherein the second compensation circuit layer surrounds the second redistribution layer, the second compensation circuit layer and the second redistribution layer are electrically insulated from each other, the second compensation circuit layer is connected to the first compensation circuit layer, and the second redistribution layer is connected to the first redistribution layer.

Abstract: Provided are an adapter board and a method for forming the same, a packaging method, and a package structure. One form of a method for forming an adapter board includes: providing a base, including an interconnect region and a capacitor region, the base including a front surface and a rear surface that are opposite each other; etching the front surface of the base, to form a first trench in the base of the interconnect region and form a second trench in the base of the capacitor region; forming a capacitor in the second trench; etching a partial thickness of the base under the first trench, to form a conductive via; forming a via interconnect structure in the conductive via; and thinning the rear surface of the base, to expose the via interconnect structure.