Patents Examined by Long Pham
  • CMP polishing pad with uniform window
    Patent number: 11633830
    Abstract: A polishing pad useful in chemical mechanical polishing comprising a polishing portion having a top polishing surface and comprising a polishing material an opening through the polishing pad, and a transparent window within the opening in the polishing pad, the transparent window being secured to the polishing pad and being transparent to at least one of magnetic and optical signals, the transparent window having a thickness and a top surface having a plurality of elements separated by interconnected recesses to provide a pattern in the top surface that includes recesses for improved deflection into a cavity in the polishing pad during polishing.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: April 25, 2023
    Assignee: Rohm and Haas Electronic Materials CMP Holdings, Inc.
    Inventors: Mauricio E. Guzman, Nestor A. Vasquez, Matthew R. Gadinski, Michael E. Mills
  • Materials and structures for optical and electrical III-nitride semiconductor devices and methods
    Patent number: 11631775
    Abstract: The present invention provides materials, structures, and methods for III-nitride-based devices, including epitaxial and non-epitaxial structures useful for III-nitride devices including light emitting devices, laser diodes, transistors, detectors, sensors, and the like. In some embodiments, the present invention provides metallo-semiconductor and/or metallo-dielectric devices, structures, materials and methods of forming metallo-semiconductor and/or metallo-dielectric material structures for use in semiconductor devices, and more particularly for use in III-nitride based semiconductor devices. In some embodiments, the present invention includes materials, structures, and methods for improving the crystal quality of epitaxial materials grown on non-native substrates.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: April 18, 2023
    Inventor: Robbie J. Jorgenson
  • Semiconductor packages including antenna pattern
    Patent number: 11626373
    Abstract: A semiconductor package having a thinner shape and including an antenna is provided. A semiconductor package comprises a first substrate, a second substrate on the first substrate and including a first face facing the first substrate and a second face opposite to the first face, a pillar extending from the second face of the second substrate to the first substrate, and a first semiconductor chip on the second face of the second substrate and connected to the pillar. The second substrate may include an antenna pattern, and the antenna pattern may be connected to the first semiconductor chip, and may be on the second face of the second substrate such that the antenna pattern is isolated from direct contact with the first semiconductor chip.
    Type: Grant
    Filed: February 10, 2021
    Date of Patent: April 11, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Se Ho You, Hyeong Seob Kim, Seung Kon Mok
  • FinFET device and methods of forming the same
    Patent number: 11626518
    Abstract: A semiconductor device includes a substrate; a fin protruding above the substrate, the fin including a compound semiconductor material that includes a semiconductor material and a first dopant, the first dopant having a different lattice constant than the semiconductor material, where a concentration of the first dopant in the fin changes along a first direction from an upper surface of the fin toward the substrate; a gate structure over the fin; a channel region in the fin and directly under the gate structure; and source/drain regions on opposing sides of the gate structure, the source/drain regions including a second dopant, where a concentration of the second dopant at a first location within the channel region is higher than that at a second location within the channel region, where the concentration of the first dopant at the first location is lower than that at the second location.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: April 11, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shahaji B. More, Shih-Chieh Chang, Cheng-Han Lee
  • Semiconductor device and manufacturing method of the semiconductor device
    Patent number: 11621274
    Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a well structure, a first channel pillar and a second channel pillar extending from an inside of the well structure in an upward direction, a semiconductor pattern coupled between the first channel pillar and the second channel pillar and having a gap disposed in a central region of the semiconductor pattern, and a source junction formed in the semiconductor pattern.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: April 4, 2023
    Assignee: SK hynix Inc.
    Inventor: Kang Sik Choi
  • Selective EMI shielding using preformed mask with fang design
    Patent number: 11616025
    Abstract: A semiconductor device has a semiconductor package including a substrate comprising a land grid array. A component is disposed over the substrate. An encapsulant is deposited over the component. The land grid array remains outside the encapsulant. A fanged metal mask is disposed over the land grid array. A shielding layer is formed over the semiconductor package. The fanged metal mask is removed after forming the shielding layer.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: March 28, 2023
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: ChangOh Kim, KyoungHee Park, JinHee Jung, OMin Kwon, JiWon Lee, YuJeong Jang
  • Microelectronic assemblies
    Patent number: 11616047
    Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a first surface and an opposing second surface; a first die having a first surface and an opposing second surface embedded in a first dielectric layer, where the first surface of the first die is coupled to the second surface of the package substrate by first interconnects; a second die having a first surface and an opposing second surface embedded in a second dielectric layer, where the first surface of the second die is coupled to the second surface of the first die by second interconnects; and a third die having a first surface and an opposing second surface embedded in a third dielectric layer, where the first surface of the third die is coupled to the second surface of the second die by third interconnects.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: March 28, 2023
    Assignee: Intel Corporation
    Inventors: Adel A. Elsherbini, Feras Eid, Johanna M. Swan, Shawna M. Liff
  • Electronic package structure and fabrication method thereof
    Patent number: 11615997
    Abstract: An electronic package structure includes: a substrate having an upper surface; a solder mask layer disposed on the upper surface of the substrate, at least one outer side of the solder mask layer being aligned with at least one outer side of the substrate; an electronic component with a first surface provided on the upper surface of the substrate; and a cavity located between the electronic component and the solder mask layer. A first surface of the cavity is formed by the first surface of the electronic component.
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: March 28, 2023
    Assignee: RichWave Technology Corp.
    Inventor: Yu-Lung Wen
  • Routing structure between dies and method for arranging routing between dies
    Patent number: 11600572
    Abstract: A routing structure between dies is provided, including a trace layer, disposed on a substrate, wherein a plurality of routing paths is embedded in the trace layer. In addition, a first die and a second die are disposed on the trace layer and connected by the routing paths. A spacing gap between the first die and the second die is along a first direction and interfacing edges of the first die and the second die are extending along a second direction perpendicular to the first direction. Each of the routing paths includes a first straight portion in parallel to connect to the interfacing edges. The first straight portion has a slant angle with respect to the first direction other than 0° and 90°.
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: March 7, 2023
    Assignees: Global Unichip Corporation, Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Chieh Liao, Hao-Yu Tung, Yu-Cheng Sun, Ming-Hsuan Wang, Igor Elkanovich
  • Three-dimensional semiconductor memory devices and methods of fabricating the same
    Patent number: 11600638
    Abstract: Disclosed are three-dimensional semiconductor memory devices and methods of fabricating the same. The method comprises sequentially forming a sacrificial pattern and a source conductive layer on a substrate, forming a mold structure including a plurality of insulating layers and a plurality of sacrificial layers on the source conductive layer; forming a plurality of vertical structures penetrating the mold structure, forming a trench penetrating the mold structure, forming a sacrificial spacer on a sidewall of the trench, removing the sacrificial pattern to form a horizontal recess region; removing the sacrificial spacer, and forming a source conductive pattern filling the horizontal recess region.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: March 7, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sanghoon Lee, Sunggil Kim, Seulye Kim, Hwaeon Shin, Joonsuk Lee, Hyeeun Hong
  • InFO coil on metal plate with slot
    Patent number: 11600431
    Abstract: A structure includes an encapsulating material, and a coil including a through-conductor. The through-conductor is in the encapsulating material, with a top surface of the through-conductor coplanar with a top surface of the encapsulating material, and a bottom surface of the through-conductor coplanar with a bottom surface of the encapsulating material. A metal plate is underlying the encapsulating material. A slot is in the metal plate and filled with a dielectric material. The slot has a portion overlapped by the coil.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: March 7, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chuei-Tang Wang, Wei-Ting Chen, Chieh-Yen Chen, Hao-Yi Tsai, Ming Hung Tseng, Hung-Yi Kuo, Chen-Hua Yu
  • Semiconductor package
    Patent number: 11594499
    Abstract: A semiconductor package including a package substrate, a connection substrate on the package substrate and having on a lower corner of the connection substrate a recession that faces a top surface of the package substrate, a semiconductor chip on the connection substrate, a plurality of first connection terminals connecting the connection substrate to the semiconductor chip, and a plurality of second connection terminals connecting the package substrate to the connection substrate. The recession is laterally spaced apart from the second connection terminals.
    Type: Grant
    Filed: March 16, 2021
    Date of Patent: February 28, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yeongkwon Ko, Un-Byoung Kang, Jaekyung Yoo, Teak Hoon Lee
  • Semiconductor device and manufacturing method of the semiconductor device
    Patent number: 11587946
    Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a well structure, a first channel pillar and a second channel pillar extending from an inside of the well structure in an upward direction, a semiconductor pattern coupled between the first channel pillar and the second channel pillar and having a gap disposed in a central region of the semiconductor pattern, and a source junction formed in the semiconductor pattern.
    Type: Grant
    Filed: September 14, 2020
    Date of Patent: February 21, 2023
    Assignee: SK hynix Inc.
    Inventor: Kang Sik Choi
  • Process control for package formation
    Patent number: 11587922
    Abstract: A method includes bonding a first and a second device die to a third device die, forming a plurality of gap-filling layers extending between the first and the second device dies, and performing a first etching process to etch a first dielectric layer in the plurality of gap-filling layers to form an opening. A first etch stop layer in the plurality of gap-filling layers is used to stop the first etching process. The opening is then extended through the first etch stop layer. A second etching process is performed to extend the opening through a second dielectric layer underlying the first etch stop layer. The second etching process stops on a second etch stop layer in the plurality of gap-filling layers. The method further includes extending the opening through the second etch stop layer, and filling the opening with a conductive material to form a through-via.
    Type: Grant
    Filed: September 21, 2020
    Date of Patent: February 21, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Fa Chen, Hsien-Wei Chen
  • Electronic package and manufacturing method thereof
    Patent number: 11587892
    Abstract: An electronic package in which at least one magnetically permeable member is disposed between a carrier and an electronic component, where the electronic component has a first conductive layer, and the carrier has a second conductive layer, such that the magnetically permeable element is located between the first conductive layer and the second conductive layer. Moreover, a plurality of conductive bumps that electrically connect the first conductive layer and the second conductive layer are arranged between the electronic component and the carrier to surround the magnetically permeable member for generating magnetic flux.
    Type: Grant
    Filed: January 27, 2021
    Date of Patent: February 21, 2023
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Chih-Hsien Chiu, Ko-Wei Chang
  • Semiconductor device and method for fabricating the same
    Patent number: 11587835
    Abstract: A method for fabricating semiconductor device includes the steps of providing a substrate having a first region and a second region, forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region, and forming a shallow trench isolation (STI) around the first fin-shaped structure and the second fin-shaped structure. Preferably, the first fin-shaped structure and the second fin-shaped structure comprise different radius of curvature and a center of curvature of the first fin-shaped structure is lower than a top surface of the STI and a center of curvature of the second fin-shaped structure is higher than the top surface of the STI.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: February 21, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chun-Jen Chen, Tien-I Wu, Yu-Shu Lin
  • Power amplifier modules with flip-chip and non-flip-chip power transistor dies
    Patent number: 11587852
    Abstract: An amplifier module includes a module substrate and first and second power transistor dies. The first power transistor die is coupled to a mounting surface of the module substrate, and has first and second input/output (I/O) contact pads and a first ground contact pad, all of which are all exposed at a surface of the first power transistor die that faces toward the mounting surface of the module substrate. The second power transistor die also is coupled to the mounting surface, and has third and fourth I/O contact pads and a second ground contact pad. The third and fourth I/O contact pads are exposed at a surface of the second power transistor die that faces away from the mounting surface of the module substrate, and the second ground contact pad is exposed at a surface of the second power transistor die that faces toward the mounting surface.
    Type: Grant
    Filed: March 18, 2021
    Date of Patent: February 21, 2023
    Assignee: NXP USA, Inc.
    Inventors: Vikas Shilimkar, Ramanujam Srinidhi Embar
  • Semiconductor package
    Patent number: 11581266
    Abstract: A semiconductor package including a substrate including at least one ground pad and a ground pattern; a semiconductor chip on the substrate; and a shield layer on the substrate and covering the semiconductor chip, wherein the shield layer extends onto a bottom surface of the substrate and includes an opening region on the bottom surface of the substrate, a bottom surface of the at least one ground pad is at the bottom surface of the substrate, a side surface of the ground pattern is at a side surface of the substrate, and the shield layer on the bottom surface of the substrate is in contact with the bottom surface of the at least one ground pad and in contact with the side surface of the ground pattern.
    Type: Grant
    Filed: March 25, 2021
    Date of Patent: February 14, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jongwan Kim, Kyong Hwan Koh, Juhyeon Oh, Yongkwan Lee
  • Complementary metal-oxide-semiconductor image sensor and method of making
    Patent number: 11581360
    Abstract: A pixel includes a workpiece having a protrusion and a bulk, wherein the protrusion extends from an upper surface of the bulk. The pixel further includes a protrusion doping region in the protrusion. The pixel further includes a photosensitive device comprising a plurality of first regions, wherein each of the plurality of first regions is in the bulk and the protrusion.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: February 14, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventor: Bo-Tsung Tsai
  • Ceramic laminated substrate, module, and method of manufacturing ceramic laminated substrate
    Patent number: 11574860
    Abstract: Provided is a ceramic laminated substrate which is formed on an electronic component to be mounted and is less likely to cause mounting defects even if there is irregularity in the height of solders. The ceramic laminated substrate includes: a ceramic laminate on which ceramic layers are laminated; via conductors; terminal electrodes; and a land electrode. The land electrode has a first land electrode and a second land electrode that are used to join different terminal electrodes of a single electronic component. The area of the first land electrode is smaller than the area of the second land electrode, and the first land electrode has a bump electrode and a plating layer, the second land electrode has a membrane electrode and plating layers, and the height of the first land electrode is formed higher than the height of the second land electrode.
    Type: Grant
    Filed: January 22, 2021
    Date of Patent: February 7, 2023
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Takuya Goitsuka