Patents Examined by Mark A Giardino, Jr.
  • Patent number: 11934674
    Abstract: Embodiments of the present disclosure relate to a method, an electronic device, and a computer program product for storing and accessing data. A method for storing data includes: dividing, in response to receiving a request for storing data from a client, the data into a plurality of data blocks; storing the plurality of data blocks in a plurality of servers respectively; generating metadata of the data to record corresponding addresses for storing the plurality of data blocks in the plurality of servers; and storing the generated metadata in a metadata repository. The embodiments of the present disclosure can effectively improve data transmission efficiency, data availability, and data security in a cloud storage system.
    Type: Grant
    Filed: October 16, 2020
    Date of Patent: March 19, 2024
    Assignee: EMC IP Holding Company LLC
    Inventors: Zhenzhen Lin, Si Chen
  • Patent number: 11922014
    Abstract: According to one embodiment, a controller of a memory system manages a first table maintaining a relationship between a logical address and a physical address, compresses first data corresponding to a first address of a write command, specifies a size of second data obtained by compressing the first data, determines allocation of the second data on a memory based on the size of the second data, stores a second address corresponding to a physical area where a head of the second data is stored and a physical area number used to store the second data in an entry of the first logical address in the first table, and stores the first address, offset of a position of a leader of the second data in the physical area, and the size of the second data in the physical area.
    Type: Grant
    Filed: September 6, 2022
    Date of Patent: March 5, 2024
    Assignee: Kioxia Corporation
    Inventors: Keiri Nakanishi, Kensaku Yamaguchi, Takashi Takemoto
  • Patent number: 11868647
    Abstract: A nonvolatile memory device includes a memory block including a memory area, an on-chip valley search (OVS) circuit performing an OVS sensing operation on the memory block, and a buffer memory storing at least one variation table including variation information of a threshold voltage of memory cells, obtained from the OVS sensing operation. A reading operation including an OVS sensing operation and a main sensing operation on the memory area is performed in response to a read command applied by a memory controller, the OVS sensing operation is performed at an OVS sensing level, and the main sensing operation is performed at a main sensing level reflecting the variation information. In the nonvolatile memory device, correction accuracy for deterioration of a word line threshold voltage may be improved, and a burden on a memory controller may be reduced.
    Type: Grant
    Filed: November 9, 2021
    Date of Patent: January 9, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Youngdeok Seo, Jinyoung Kim, Sehwan Park, Ilhan Park
  • Patent number: 11868661
    Abstract: An apparatus having counters for sub-addresses in segments of row address to count activation commands applied to row addresses including the sub-addresses. The counters are configured to count activation commands applied to row addresses containing the sub-addresses in accessing rows of memory cells in a memory device; For example, in response to an activation command applied to a row address having first sub-addresses, counts stored in a portion of the counters corresponding to the first sub-addresses are increased for the count of the activation command. For each respective segment, counts stored in counters for sub-addresses in the respective segment are used to determine whether at least one of the sub-addresses has seen more activation commands than a threshold. An alert is generated for risk mitigation operations in response to each segment having at least one sub-address that has seen more activation commands than the threshold.
    Type: Grant
    Filed: May 17, 2022
    Date of Patent: January 9, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Kai Wang
  • Patent number: 11861198
    Abstract: Techniques are provided for journal replay optimization. A distributed storage architecture can implement a journal within memory for logging write operations into log records. Latency of executing the write operations is improved because the write operations can be responded back to clients as complete once logged within the journal without having to store the data to higher latency disk storage. If there is a failure, then a replay process is performed to replay the write operations logged within the journal in order to bring a file system up-to-date. The time to complete the replay of the write operations is significantly reduced by caching metadata (e.g., indirect blocks, checksums, buftree identifiers, file block numbers, and consistency point counts) directly into log records. Replay can quickly access this metadata for replaying the write operations because the metadata does not need to be retrieved from the higher latency disk storage into memory.
    Type: Grant
    Filed: April 25, 2022
    Date of Patent: January 2, 2024
    Assignee: NetApp, Inc.
    Inventors: Kevin Daniel Varghese, Ananthan Subramanian, Asif Imtiyaz Pathan
  • Patent number: 11853610
    Abstract: A storage device for providing data storage services to a host includes persistent storage for storing a file and a controller. The controller obtains a write request from the host for the file, the write request comprises a command packet; perform processing of the command packet using a payload portion of the file; generate a response packet based on the processing of the command packet; and store the response packet in a response portion of the file in response to the write request.
    Type: Grant
    Filed: February 11, 2022
    Date of Patent: December 26, 2023
    Assignee: iodyne, LLC
    Inventor: Michael W. Shapiro
  • Patent number: 11848043
    Abstract: A memory device includes memory cells connected to a first word-line, wherein the memory cells include a data region in which data is stored and a counting value backup region in which the number of times the first word-line is activated is backed up, a counting table for storing a first row address corresponding to the first word-line and a first counting value as a counting result of the number of times the first word-line is activated, and a comparator configured to compare the first counting value with a first backed-up counting value stored in the counting value backup region; and when the first counting value is greater than the first backed-up counting value, back up the first counting value in the counting value backup region, or when the first backed-up counting value is greater than the first counting value, overwrite the first backed-up counting value into the counting table.
    Type: Grant
    Filed: March 8, 2022
    Date of Patent: December 19, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung Min You, Ho-Youn Kim, Won-Hyung Song, Hi Jung Kim
  • Patent number: 11836377
    Abstract: Data from a host system is received at a memory device, where the memory device includes a primary region to initially store the data received from the host system and one or more secondary regions to store data transferred from the primary region. A write operation is performed on one or more write units of the primary region with the data received from the host system, where a write unit of the primary region has lower density blocks than a write unit of the secondary region. Whether a subset of write units of the primary region corresponding to a pre-determined number of write units is written with at least a portion of the data received from the host system is determined. In response to determining that the subset of write units of the primary region is written, another write operation is performed on at least one write units of the secondary region with respective data of the subset of write units of the primary region.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: December 5, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Abdelhakim Alhussien, Ayberk Ozturk, Karl D. Schuh, Luca Bert
  • Patent number: 11836346
    Abstract: A memory array arranged as a plurality of memory cells. The memory cells are configured to operate at a determined voltage. A memory management circuitry coupled to the plurality of memory cells tags a first set of the plurality of memory cells as low-voltage cells and tags a second set of the plurality of memory cells as high-voltage cells. A power source provides a low voltage to the first set of memory cells and provides a high voltage to the second set of memory cells based on the tags.
    Type: Grant
    Filed: May 12, 2022
    Date of Patent: December 5, 2023
    Assignees: STMICROELECTRONICS S.r.l., STMicroelectronics International N.V.
    Inventors: Nitin Chawla, Giuseppe Desoli, Anuj Grover, Thomas Boesch, Surinder Pal Singh, Manuj Ayodhyawasi
  • Patent number: 11836386
    Abstract: In a multi controller storage system, hardware and software are updated without interruption. The storage system including a node has storage control units each including a processor, a memory, and a port; and a storage drive, and the storage control units each request data access and transmit and receive data with respect to a host computer via the ports. The processors process input and output data from the host computer, the memories store the control information in order to access the data stored in the storage drive, and the storage system transmits the control information stored in the memories to another node, stores the control information in the memories of the storage control units, and sets ports of the other node in consideration of a relationship between the storage control units and the ports of the nodes, if the other node can access data relating to the control information.
    Type: Grant
    Filed: August 5, 2022
    Date of Patent: December 5, 2023
    Assignee: HITACHI, LTD.
    Inventors: Ryosuke Tatsumi, Akira Yamamoto, Kazuki Matsugami
  • Patent number: 11829757
    Abstract: There are provided systems and methods for a multi-layer cache to prevent user experience interrupts during feature flag management. A service provider may provide applications to computing devices of users including mobile applications. Use and availability of features in an application may be configured using feature flags, however, change of these feature flags may initiate an application refresh that affects user experiences with the application. To prevent interruptions, a multi-layer data cache may be used where feature flag data for the feature flags may initially be loaded, after a time period, to a first layer cache that is not used to update the application. When conditions exist for updating the application without affecting the user experience, such as if the user is no longer using a workflow, the feature flag data may be loaded to a second layer cache. The second layer cache may then be used for updating.
    Type: Grant
    Filed: December 29, 2021
    Date of Patent: November 28, 2023
    Assignee: Brex Inc.
    Inventors: Ming Xiao, Kingsley Ochu
  • Patent number: 11822825
    Abstract: A distributed cloud-based storage system, where the distributed cloud-based storage system includes: receiving, by one or more storage controller applications of the cloud-based storage system, one or more storage operations; storing, among one or more cloud computing instances of the cloud-based storage system, the one or more storage operations; and distributing, among one or more cloud computing instances within respective one or more cloud computing environments within distinct geographic regions, one or more of the one or more storage operations.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: November 21, 2023
    Assignee: PURE STORAGE, INC.
    Inventors: Naveen Neelakantam, Joshua Freilich
  • Patent number: 11809717
    Abstract: A method, an electronic device, and a computer program product for data management is disclosed. The method includes receiving a request for performing, on data, a first management operation related to a first storage device, the request indicating a type of the data. The method further includes determining a first service associated with the type of the data and enabling the first service to perform the first management operation on the data. Thus, resource consumption of a data manager at runtime may be substantially reduced, which saves resources to reduce operating cost of the data manager, and improves the user experience of users who use the data manager.
    Type: Grant
    Filed: April 21, 2021
    Date of Patent: November 7, 2023
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Weiyang Liu, Lihui Su, Min Liu, Qi Wang, Ming Zhang
  • Patent number: 11809295
    Abstract: A node mode adjustment method for when a storage cluster BBU fails and related component. The storage cluster comprises multiple IO GROUPs; each IO GROUP comprises two nodes, and each node is connected to a corresponding BBU of the node. The method comprises: monitoring the status of each BBU in the storage cluster; after detecting that any one BBU has failed, when it is determined that the BBU connected to the peer node of the node to which the failed BBU is connected has not failed, and it is determined that the storage cluster is not downgraded, maintaining in a write-back mode the node connected to the BBU detected to have failed and the peer node of said node. Applying the solution of the present application will help to ensure that the storage cluster has the advantages of high availability and high IO performance.
    Type: Grant
    Filed: January 21, 2020
    Date of Patent: November 7, 2023
    Assignee: Inspur Suzhou Intelligent Technology Co., Ltd.
    Inventor: Minggang Sun
  • Patent number: 11809311
    Abstract: Devices and techniques are disclosed herein for allowing host-based maintenance of a flash memory device. In certain examples, memory write information can be encrypted at the memory device and provided to the host for updating and maintaining memory device maintenance statistics.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: November 7, 2023
    Assignee: Micron Technology, Inc.
    Inventors: David Aaron Palmer, Christian M. Gyllenskog, Jonathan Scott Parry, Stephen Hanna
  • Patent number: 11797193
    Abstract: The disclosure provides an error detection method for a memory device, wherein the memory device comprises a plurality of memory blocks, and each of the memory blocks has a plurality of word lines connected to a plurality of memory cells, the error detection method comprises the following steps. Performing a plurality of times of programming operations on the memory cells connected to each of the word lines to program the memory cells as a plurality of programming-level states. Performing a plurality of times of verifying operations on the memory cells to verify the programming-level states respectively. When the number of verifications of the verifying operations for one of the programming-level states is greater than an upper limit number corresponding to the one of the programming-level states, marking the word line as an error word line.
    Type: Grant
    Filed: January 4, 2022
    Date of Patent: October 24, 2023
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Shih-Chung Lee
  • Patent number: 11789624
    Abstract: An apparatus comprises at least one processing device that includes a processor coupled to a memory. The processing device is configured to control delivery of input-output operations from a host device to at least first and second storage systems over selected ones of a plurality of paths through a network, to detect a single point of failure condition relating to a given one of the paths to a particular logical storage device in one of the first and second storage systems, and to determine whether or not the particular logical storage device is accessible in another one of the first and second storage systems. Different types of notifications are generated by the processing device depending on whether or not the particular logical storage device is accessible in the other one of the first and second storage systems.
    Type: Grant
    Filed: May 31, 2022
    Date of Patent: October 17, 2023
    Assignee: Dell Products L.P.
    Inventors: Vinay G. Rao, Sanjib Mallick, Arieh Don
  • Patent number: 11782609
    Abstract: Provided is a method for auditing an abnormality of a block device in a cloud platform. By automatically auditing abnormal data of a path layer and a multipath layer, the accuracy of multipath and path information on a host and whether a link has a fault may be quickly analyzed, operation and maintenance personnel may discover problems as soon as possible, the problem troubleshooting steps are simplified, the operation and maintenance personnel are liberated from complex work of manual troubleshooting, the troubleshooting capability of a cloud computing platform is improved, the work of the operation and maintenance personnel is simplified, and the problems are rapidly positioned.
    Type: Grant
    Filed: February 24, 2021
    Date of Patent: October 10, 2023
    Assignee: INSPUR SUZHOU INTELLIGENT TECHNOLOGY CO., LTD.
    Inventors: Yandong Xuan, Kaiyuan Qi, Bao Ma, Dong Zhang
  • Patent number: 11782608
    Abstract: Methods, systems, and devices for error information signaling for memory are described. A memory device may perform an error detection procedure while in a power-saving mode. Upon detecting an error, the memory device may indicate the error to a host device. In response to indicating the error, the memory device may receive a command to exit the power-saving mode. The memory device may comply with the command and exit the power-saving mode by enabling one or more interfaces of the memory device. The memory device may receive a request for error information over the one or more interfaces and, in response to the request, may transmit the error information to the host device.
    Type: Grant
    Filed: May 20, 2022
    Date of Patent: October 10, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Michael Dieter Richter, Thomas Hein, Casto Salobrena Garcia
  • Patent number: 11775191
    Abstract: A data storage device including, in one implementation, a non-volatile memory device including a memory block that includes a plurality of memory dies and a controller that is coupled to the non-volatile memory device and that allocates power to non-memory components based on a determined usage of the memory dies. The controller is configured to monitor a utilization of the plurality of memory dies, determine a utilization state of the plurality of memory dies, and calculate an amount of available power allocated to the plurality of memory dies in response to determining that the plurality of memory dies are in a low utilization state. The controller is also configured to determine whether the amount of available power is above a predetermined threshold, and reallocate the available power to one or more components within the data storage device in response to determining that the amount of available power is above the predetermined threshold.
    Type: Grant
    Filed: June 2, 2022
    Date of Patent: October 3, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Amit Sharma, Abhinandan Venugopal, Dinesh Kumar Agarwal, Akhilesh Yadav