Abstract: A bipolar junction transistor (LBJT) device that includes a base region of a first III-V semiconductor material having A first band gap; and emitter and collector regions present on opposing sides of the base region, wherein the emitter and collector regions are comprised of a second III-V semiconductor material having a wider band gap than the first III-V semiconductor material. A dielectric region is present underlying the base region, emitter region and the collect region. The dielectric region has an inverted apex geometry. The sidewalls of dielectric region that extend to the apex of the inverted apex geometry are present on facets of a supporting substrate III-V semiconductor material having a {110} crystalline orientation.

Abstract: A sensor package structure includes a substrate, a sensor chip disposed on the substrate, a plurality of wires electrically connected to the substrate and the sensor chip, a transparent layer facing the sensor chip, a support disposed on the substrate, and a packaging compound disposed on the substrate and covering side edges of the support and the transparent layer. A part of each wire is embedded in the support. A height from the upper surface of the substrate to the top of the support is larger than a height from the upper surface of the substrate to the top of any of the wires. The bottom surface of the transparent layer has a central region facing the sensor chip and a ring-shaped supporting region surrounded by the central region. The support is arranged outside the sensor chip and abuts against the supporting region.

Abstract: The disclosure provides methods and apparatus for release-assisted microcontact printing of MEMS. Specifically, the principles disclosed herein enable patterning diaphragms and conductive membranes on a substrate having articulations of desired shapes and sizes. Such diaphragms deflect under applied pressure or force (e.g., electrostatic, electromagnetic, acoustic, pneumatic, mechanical, etc.) generating a responsive signal. Alternatively, the diaphragm can be made to deflect in response to an external bias to measure the external bias/phenomenon. The disclosed principles enable transferring diaphragms and/or thin membranes without rupturing.

Abstract: Semiconductor devices and method of forming the same include forming a stack of vertically aligned, alternating layers including sacrificial layers and channel layers. The sacrificial layers are recessed relative to the channel layers to form recesses. A dual-layer dielectric is deposited. The dual-layer dielectric includes a first dielectric material formed conformally on surfaces of the recesses and a second dielectric material filling a remainder of the recesses. The first dielectric material is recessed relative to the second dielectric material. The second dielectric material is etched away to create air gaps. Outer spacers are formed using a third dielectric material that pinches off, preventing the third dielectric material from filling the air gaps.

Abstract: A method for forming a memory device that includes providing a free layer of an alloy of cobalt (Co), iron (Fe) and boron (B) overlying a reference layer; and forming metal layer comprising a boron (B) sink composition atop the free layer. Boron (B) may be diffused from the free layer to the metal layer comprising the boron sink composition. At least a portion of the metal layer including the boron (B) sink composition is removed. A metal oxide is formed atop the free layer. The free layer may be a crystalline cobalt and iron alloy. An interface between the metal oxide and free layer can provide perpendicular magnetic anisotropy character.

Abstract: A semiconductor device includes a semiconductor substrate having a plurality of Hall elements formed therein, and a magnetic body formed on the semiconductor substrate and having a magnetic flux converging function. The contour in a vertical cross section of the magnetic body on the semiconductor substrate has an outer circumferential portion. At least a part of the outer circumferential portion has a curve-shaped portion and a portion substantially parallel to the semiconductor substrate. A gap is formed between the semiconductor substrate and the portion of the magnetic body that is substantially parallel to the semiconductor substrate, and the gap lies above the entire top surfaces of the Hall elements. The magnetic body has at least a part of a structure made of non-magnetic substance embedded therein.

Abstract: A semiconductor device includes a substrate, an isolation structure over the substrate, two fins over the substrate and protruding out of the isolation structure, and an epitaxial feature over the two fins. The epitaxial feature includes two lower portions and one upper portion. The two lower portions are over the two fins respectively. The upper portion is over the two lower portions and connects the two lower portions. The upper portion has a different dopant concentration than the two lower portions. A top surface of the upper portion is substantially flat.

Abstract: A semiconductor comprising at least one contact, formed on an interface with the semiconductor, the contact comprising at least a layer of a first metal, the first metal being of sufficient amount to impart a first property in the layer; and a second metal diffused in the layer, the second metal having a concentration in the layer sufficiently low such that the second metal does not diminish significantly the first property of the layer, the concentration being sufficiently high such that the second metal imparts significantly a second property in the layer.

Abstract: A trench-gate semiconductor device including an outside trench, increases reliability of an insulating film at a corner of an open end of the outside trench. The semiconductor device includes: a gate trench reaching an inner part of an n-type drift layer in a cell region; an outside trench outside the cell region; a gate electrode formed inside the gate trench through a gate insulating film; a gate line formed inside the outside trench through an insulating film; and a gate line leading portion formed through the insulating film to cover a corner of an open end of the outside trench closer to the cell region, and electrically connecting the gate electrode to the gate line, and the surface layer of the drift layer in contact with the corner has a second impurity region of p-type that is a part of the well region.

Abstract: According to one embodiment, a magnetic memory device includes a first magnetic portion extending in a first direction, a first magnetic layer, and a first nonmagnetic layer provided between the first magnetic layer and a portion of the first magnetic portion. The first magnetic portion has a first surface. The first surface includes bottom portions, and top portions. The bottom portions and the top portions are arranged alternately in the first direction. The bottom portions include a first bottom portion, a second bottom portion adjacent to the first bottom portion in the first direction, a third bottom portion, and a fourth bottom portion adjacent to the third bottom portion in the first direction. The top portions include a first top portion provided between the first bottom portion and the second bottom portion, and a second top portion provided between the third bottom portion and the fourth bottom portion.

Abstract: A multi-gate high electron mobility transistor (HEMT) and its methods of formation are disclosed. The multi-gate HEMT includes a substrate and an adhesion layer on top of the substrate. A channel layer is disposed on top of the adhesion layer, and a first gate electrode is disposed on top of the channel layer. The first gate electrode has a first gate dielectric layer in between the first gate electrode and the channel layer. A second gate electrode is embedded within the substrate and beneath the channel layer. The second gate electrode has a second gate dielectric layer completely surrounding the second gate electrode. A pair of source and drain contacts are disposed on opposite sides of the first gate electrode.

Abstract: The present disclosure relates to a solid-state image pickup apparatus and an electronic apparatus capable of preventing charges accumulated in a PD from being lost and suppressing reductions of an S/N and a dynamic range. The apparatus according to an embodiment of the present disclosure includes: a photoelectric conversion unit; a first holding unit that holds the charge transferred from the photoelectric conversion unit; a first transfer gate unit that controls the transfer of the charge; a charge drain unit that is a drain destination of the charge generated by the photoelectric conversion unit; a first drain gate unit that controls the transfer of the charge from the photoelectric conversion unit to the charge drain unit; and a second drain gate unit that connects the charge drain unit with a constant voltage source. The present disclosure can be applied to a CIS and an electronic apparatus provided with the CIS.

Abstract: An electronic device includes a substrate, a functional element that is arranged on the substrate, a terminal that is arranged on the substrate and that is electrically connected to the functional element, and a bonding wire that is connected to the terminal. The terminal has an alloy portion that is alloyed to the bonding wire at a connection portion between the terminal and the bonding wire, and the thickness of the terminal is larger than the thickness of the alloy portion. Moreover, the terminal is formed of the same material (silicon) as the functional element.

Abstract: A gas sensor includes a p-type semiconductor layer that contains copper or silver cations and contacts with detection target gas, a first electrode that is a Schottky electrode to the p-type semiconductor layer, a high-resistance layer that is provided between the p-type semiconductor layer and the first electrode such that the p-type semiconductor layer and the first electrode partly contact with each other and has resistance higher than that of each of the p-type semiconductor layer and the first electrode, and a second electrode that is an ohmic electrode to the p-type semiconductor layer.

Abstract: A method for forming a memory device that includes providing a free layer of an alloy of cobalt (Co), iron (Fe) and boron (B) overlying a reference layer; and forming metal layer comprising a boron (B) sink composition atop the free layer. Boron (B) may be diffused from the free layer to the metal layer comprising the boron sink composition. At least a portion of the metal layer including the boron (B) sink composition is removed. A metal oxide is formed atop the free layer. The free layer may be a crystalline cobalt and iron alloy. An interface between the metal oxide and free layer can provide perpendicular magnetic anisotropy character.

Abstract: The present disclosure discloses in embodiments a thin film transistor and a manufacturing method thereof, an array substrate. The thin film transistor comprises: a base substrate, an active layer, a source, a gate, and a drain. Two ends of the active layer are connected to the source and the drain, respectively. The gate comprises a top gate and a bottom gate arranged opposite to each other in a direction perpendicular to the base substrate, the top gate comprising a top gate top portion and a top gate side portion connected to the top gate top portion, the top gate side portion extending from the top gate top portion towards the base substrate. The active layer is sandwiched between the top gate top portion and the bottom gate. A sidewall of the active layer is at least partially surrounded by the top gate side portion.

Abstract: A semiconductor device includes a fin extending along a first direction over a substrate, and a gate structure extending in a second direction overlying the fin. The gate structure includes a gate dielectric layer overlying the fin, a gate electrode overlying the gate dielectric layer, and insulating gate sidewalls on opposing lateral surfaces of the gate electrode extending along the second direction. A source/drain region is formed in the fin in a region adjacent the gate electrode structure, and a stressor layer is between the source/drain region and the semiconductor substrate. The stressor layer includes GeSn or SiGeSn containing 1019 atoms cm?3 or less of a dopant, and a portion of the fin under the gate structure is a channel region.

Abstract: This disclosure discloses a display panel, a production method thereof, and a display apparatus. This method comprises: forming a pattern of a first metal layer on a base substrate and a pattern of a metal oxide conductive layer being electrically connected to the first metal layer by at least one through hole at a side of the first metal layer away from the base substrate; forming a reductive metal compound layer on a surface of the first metal layer at a side away from the base substrate before forming the pattern of the metal oxide conductive layer; treating the reductive metal compound layer and the metal oxide conductive layer after forming the pattern of the metal oxide conductive layer so that the reductive metal compound layer is oxidized into a second metal layer and metal particles are produced at the surface of the metal oxide conductive layer.

Abstract: A semiconductor device includes stripe-shaped trench gate structures that extend in a semiconductor body along a first horizontal direction. Transistor mesas between neighboring trench gate structures include body regions and source zones, wherein the body regions form first pn junctions with a drift structure and second pn junctions with the source zones. The source zones directly adjoin two neighboring trench gate structures, respectively. Diode mesas that include at least portions of diode regions form third pn junctions with the drift structure. The diode mesas directly adjoin two neighboring trench gate structures, respectively. The transistor mesas and the diode mesas alternate at least along the first horizontal direction.

Abstract: In an equal width active cell IE type IGBT, a wide active cell IE type IGBT, and the like, an active cell region is equal in trench width to an inactive cell region, or the trench width of the inactive cell region is narrower. Accordingly, it is relatively easy to ensure the breakdown voltage. However, with such a structure, an attempt to enhance the IE effect entails problems such as further complication of the structure. The present invention provides a narrow active cell IE type IGBT having an active cell two-dimensional thinned-out structure, and not having a substrate trench for contact.