Patents Examined by Michael Krofcheck
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Patent number: 11237957Abstract: A realm management unit (RMU) 20 manages ownership of memory regions by realms, each realm corresponding to at least a portion of a software process executed by processing circuitry. Memory access circuitry 26 enforces ownership rights for the regions, with the owner realm having a right to exclude other realms from accessing data stored within its owned region. The RMU 20 controls transitions of memory regions between region states, including an invalid state 220, a valid state 222, and a scrub-commit state 800 in which the memory region is allocated to an owner realm, inaccessible to that owner realm until a scrubbing process has been performed for the memory region to set each storage location of the region to a value uncorrelated with a previous value stored in the storage location, and prevented from being reallocated to a different owner realm.Type: GrantFiled: October 11, 2018Date of Patent: February 1, 2022Assignee: Arm LimitedInventors: Jason Parker, Djordje Kovacevic, Gareth Rhys Stockwell, Matthew Lucien Evans
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Patent number: 11237734Abstract: An apparatus having memory dies with a memory cell array divided into a plurality of data segments. A stagger circuit selects a common command signal and sets a column access signal to select a data segment to be accessed based on the common command signal and/or an individual command signal to perform a memory operation corresponding to the selected common command signal on the selected data segment. A data bus connects the memory cell arrays to form data units with each data unit including a data segment from each memory cell array and configured such that the data segments are connected in parallel to the data bus and use a same line of the data bus. The stagger circuits are configured such that data segments identified for activation in the plurality of memory dies are not part of a same data unit.Type: GrantFiled: August 19, 2019Date of Patent: February 1, 2022Assignee: Micron Technology, Inc.Inventor: Yuan He
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Patent number: 11232044Abstract: According to one embodiment, a data storage apparatus includes a controller with a data protection function. The controller manages first and second personal identification data. The first personal identification data only includes authority to request inactivation of the data protection function. The second personal identification data includes authority to request inactivation of the data protection function and activation of the data protection function. The controller permits setting of the first personal identification data, when the second personal identification data is used for successful authentication and the first personal identification data is an initial value, or when the data protection function is in an inactive state.Type: GrantFiled: October 24, 2019Date of Patent: January 25, 2022Assignee: Toshiba Memory CorporationInventors: Hiroshi Isozaki, Koichi Nagai
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Patent number: 11231860Abstract: The described technology is generally directed towards mapping doubly mapped storage clusters to resources of a real storage cluster in a way that provides high performance. In one aspect, the doubly mapped storage clusters are divided into logical columns, with each logical column corresponding to a doubly mapped node, and having a column height corresponding to a number of storage resources (e.g., disks multiplied by disk extents) managed by that doubly mapped node. The columns are logically positioned within a logical profile having dimensions of the real storage cluster. For example, the logical columns can be selected based on column height, and placed in the logical profile based on free disk extents of the nodes, greatest number of free disk extents first. Once logically positioned, the logical columns in the logical rectangle establish the mapping (e.g., embodied in a mapping table) that results in high performance.Type: GrantFiled: January 17, 2020Date of Patent: January 25, 2022Assignee: EMC IP HOLDING COMPANY LLCInventors: Mikhail Danilov, Yohannes Altaye
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Patent number: 11228647Abstract: According to various embodiments, systems and methods are provided that relate to shared access to Storage Area Networks (SAN) devices. In one embodiment, a Storage Area Network (SAN) host is provided, comprising: a server component: a first host bus adapter configured to be connected to a SAN client over a first SAN; a second host bus adapter configured to be connected to a SAN storage device over a second SAN; and wherein the server component is configured to manage a data block on the SAN storage device, receive a storage operation request from the SAN client through the first host bus adapter, and in response to the storage operation request, perform a storage operation on the data block, the storage operation being performed over the second SAN through the second host bus adapter.Type: GrantFiled: February 13, 2020Date of Patent: January 18, 2022Assignee: Commvault Systems, Inc.Inventors: Manoj Kumar Vijayan, Srikant Viswanathan, Deepak Raghunath Attarde, Varghese Devassy, Rajiv Kottomtharayil
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Patent number: 11226756Abstract: Transferring data between a first storage device coupled to a host computing system and a second storage device coupled to the first storage device includes the first storage device receiving a command from the host computing system, the first storage device determining if the command is an out-of-band (OOB) storage command, and, if the command is an OOB storage command, the first storage device sending a command to the second storage device to cause data to be transferred directly between the first storage device and the second storage device independent of the host computing system. Transferring data between a first storage device coupled to a host computing system and a second storage device coupled to the first storage device may also include the first storage device emulating a host computing system in connection with communicating with the second storage device. The second storage device may be a tape emulation unit.Type: GrantFiled: July 26, 2018Date of Patent: January 18, 2022Assignee: EMC IP Holding Company LLCInventor: Douglas E. LeCrone
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Patent number: 11226738Abstract: Disclosed are an electronic device and a data compression method thereof. According to a data compression method of an electronic device of the present invention, the method comprises the steps of: compressing a page; determining whether data included in the compressed page is stored in a memory; and merging the compressed page with data previously stored in the memory when a result of the determination shows that the data included in the compressed page is the same as the previously stored data. Therefore, the electronic device can prevent a page including the same or similar data from being stored a multiple number of times in a swap area, thereby raising memory securing efficiency.Type: GrantFiled: August 4, 2016Date of Patent: January 18, 2022Assignee: Samsung Electronics Co., Ltd.Inventors: Sangbok Han, Jinkyu Koo, Hyunsik Kim, Sunho Moon, Chungsuk Han
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Patent number: 11210218Abstract: A method for memory address mapping in a disaggregated memory system includes receiving an indication of one or more ranges of host physical addresses (HPAs) from a compute node of a plurality of compute nodes, the one or more ranges of HPAs including a plurality of memory addresses corresponding to different allocation slices of the disaggregated memory pool that are allocated to the compute node. The one or more ranges of HPAs are converted into a contiguous range of device physical addresses (DPAs). For each DPA, a target address decoder (TAD) is identified based on a slice identifier and a slice-to-TAD index. Each DPA is mapped to a media-specific physical element of a physical memory unit of the disaggregated memory pool based on the TAD.Type: GrantFiled: September 3, 2020Date of Patent: December 28, 2021Assignee: Microsoft Technology Licensing, LLCInventors: Siamak Tavallaei, Ishwar Agarwal, Vishal Soni
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Patent number: 11204698Abstract: A memory controller controls a memory device including a plurality of memory cells. The memory controller may include a workload determination circuit configured to determine a workload state indicating an operating pattern of the memory device based on optimal read voltages for reading the plurality of memory cells when a read operation performed on the memory cells fails; and an operating environment setting circuit configured to set an operating environment of the memory device based on the workload state.Type: GrantFiled: August 15, 2019Date of Patent: December 21, 2021Assignee: SK hynix Inc.Inventor: Su Jin Lim
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Patent number: 11204866Abstract: A first thread of a garbage collector can determine fields, in class metadata assigned to objects contained in a local memory, that are self-referencing fields. For a plurality of the objects, recursively, the first thread can determine whether the object has at least one child object, indicated by a self-referencing field of the object, that has not been assigned to a destination cache or a previously generated source cache. If so, the first thread can assign the child object to the destination cache to indicate that the child object is live. The first thread can add the destination cache to a global scan queue as a source cache. A second thread of the garbage collector can initiate object scanning on objects indicated in the first source cache. Memory locations where live objects are not located can be reclaimed.Type: GrantFiled: December 23, 2020Date of Patent: December 21, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Aleksandar Micic, Salman Zia Rana
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Patent number: 11194714Abstract: A first thread of a garbage collector can determine fields, in class metadata assigned to objects contained in a local memory, that are self-referencing fields. For a plurality of the objects, recursively, the first thread can determine whether the object has at least one child object, indicated by a self-referencing field of the object, that has not been assigned to a destination cache or a previously generated source cache. If so, the first thread can assign the child object to the destination cache to indicate that the child object is live. The first thread can add the destination cache to a global scan queue as a source cache. A second thread of the garbage collector can initiate object scanning on objects indicated in the first source cache. Memory locations where live objects are not located can be reclaimed.Type: GrantFiled: March 31, 2020Date of Patent: December 7, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Aleksandar Micic, Salman Zia Rana
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Patent number: 11194728Abstract: Systems, apparatuses, and methods related to memory management are described. For example, these may include a first memory level including memory pages in a memory array, a second memory level including a cache, a pre-fetch buffer, or both, and a memory controller that determines state information associated with a memory page in the memory array targeted by a memory access request. The state information may include a first parameter indicative of a current activation state of the memory page and a second parameter indicative of statistical likelihood (e.g., confidence) that a subsequent memory access request will target the memory page. The memory controller may disable storage of data associated with the memory page in the second memory level when the first parameter associated with the memory page indicates that the memory page is activated and the second parameter associated with the memory page is greater than or equal to a threshold.Type: GrantFiled: July 29, 2019Date of Patent: December 7, 2021Assignee: Micron Technology, Inc.Inventor: David Andrew Roberts
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Memory controller and operating method for performing garbage collection operation in memory devices
Patent number: 11194712Abstract: A memory controller for controlling a memory device including memory blocks is provided. The memory controller includes: a garbage collection state determiner in communication with a host device and configured to receive a garbage collection state request from the host device and determine whether the memory device is in a state that garbage collection is necessary and a block information storage unit in communication with the garbage collection state determiner and configured to receive, from the memory device, bad block generation information including a number of bad blocks included in the memory device that are unable to store data, and store block information including a total number of the memory blocks, the number of bad blocks, and a number of free blocks included in the memory device that are assigned for garbage collection.Type: GrantFiled: October 8, 2019Date of Patent: December 7, 2021Assignee: SK hynix Inc.Inventors: Mi Hee Lee, Dae Gyu Ha, Ho Ryong You -
Patent number: 11175999Abstract: A determination is made that a point-in-time copy of a consistency group of a production volume has to be stored in a backup storage that is configured to store a plurality of point-in-time copies generated at a plurality of time instants. An extent of a thin provisioned volume of a highest storage tier of a tiered storage is allocated to store the point-in-time copy of the consistency group. A process is initiated for storing the point-in-time copy of the consistency group to the extent of the highest storage tier of the tiered storage.Type: GrantFiled: September 6, 2018Date of Patent: November 16, 2021Assignee: International Business Machines CorporationInventors: Clint A. Hardy, Nicolas M. Clayton, Yang Liu, Gail Spear
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Patent number: 11169719Abstract: A method, computer program product, and computing system for generating, via a computing device, a virtual storage appliance template file. The virtual storage appliance template file may be duplicated to generate a plurality of virtual storage appliance configuration files. A plurality of virtual storage appliance nodes may be deployed, via a hypervisor, with the plurality of virtual storage appliance node configuration files. Each of the plurality of virtual storage appliance node configuration files may be configured for a respective virtual storage appliance node of the plurality of virtual storage appliance nodes.Type: GrantFiled: August 1, 2019Date of Patent: November 9, 2021Assignee: EMC IP HOLDING COMPANY, LLCInventors: Jared C. Lyon, Wai C. Yim, Susan R. Young, Michael L. Burriss, Derek Michael Scott
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Patent number: 11163470Abstract: Techniques manage a redundant array of independent disks. Such techniques involve: obtaining information on a wear level associated with each of a plurality of disks; selecting, based on the information on the wear level, a group of disks from the plurality of disks, a difference between the wear levels of any two of the group of disks being below a predetermined threshold; and creating a RAID with extents from the selected group of disks. Such techniques can sufficiently utilize the wear level to balance the data storage distribution among redundant arrays of independent disks, thereby enabling efficient management of redundant arrays of independent disks.Type: GrantFiled: October 16, 2019Date of Patent: November 2, 2021Assignee: EMC IP Holding Company LLCInventors: Xiongcheng Li, Xinlei Xu, Geng Han
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Patent number: 11157185Abstract: A method, computer program product, and computer system for identifying, by a computing device, a plurality of blocks. A maximum number of blocks of the plurality of blocks capable of being copied to a new block may be identified. Data from the maximum number of blocks of the plurality of blocks may be copied to the new block.Type: GrantFiled: July 29, 2019Date of Patent: October 26, 2021Assignee: EMC IP Holding Company, LLCInventors: Alex Soukhman, Uri Shabi
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Patent number: 11151043Abstract: Systems, apparatuses, and methods for predictive memory access are described. Memory control circuitry instructs a memory array to read a data block from or write the data block to a location targeted by a memory access request, determines memory access information including a data value correlation parameter determined based on data bits used to indicate a raw data value in the data block and/or an inter-demand delay correlation parameter determined based on a demand time of the memory access request, predicts that read access to another location in the memory array will subsequently be demanded by another memory access request based on the data value correlation parameter and/or the inter-demand delay correlation parameter, and instructs the memory array to output another data block stored at the other location to a different memory level that provides faster data access speed before the other memory access request is received.Type: GrantFiled: August 12, 2019Date of Patent: October 19, 2021Assignee: Micron Technology, Inc.Inventor: David Andrew Roberts
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Patent number: 11151032Abstract: A computer-implemented method for synchronizing local caches is disclosed. The method may include receiving a content update which is an update to a data entry stored in local caches of each of a plurality of remote servers. The method may include transmitting the content update to a first remote server to update a corresponding data entry in a local cache of the first remote server. Further, the method may include generating an invalidation command, indicating the change in the corresponding data entry. The method may include transmitting the invalidation command from the first remote server to the message server. The method may include generating, by the message server, a plurality of partitions based on the received invalidation command. The method may include transmitting, from the message server to each of the remote servers, the plurality of partitions, so that the remote servers update their respective local caches.Type: GrantFiled: December 14, 2020Date of Patent: October 19, 2021Assignee: Coupang Corp.Inventors: Seokhyun Kim, Yixiang Huang
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Patent number: 11150820Abstract: Provided is a storage system and a storage management method, aiming at reducing data movement amount necessary for using an expanded capacity in a distributed RAID. When only A (A is a positive integer) physical storage drives are added, a storage controller selects virtual parcels that are mapped to different physical storage drives among N physical storage drives and are included in different virtual chunks, changes an arrangement of the selected virtual parcels to the added A physical storage drives, and constitutes a new chunk based on unallocated virtual parcels selected from different physical storage drives among the (N+A) physical storage drives.Type: GrantFiled: September 16, 2020Date of Patent: October 19, 2021Assignee: HITACHI, LTD.Inventors: Hiroki Fujii, Yoshinori Ohira, Takeru Chiba, Yoshiaki Deguchi