Abstract: A method for accessing a binary data vector in a memory unit comprising a plurality of memory banks in which the binary data vector is stored in portions includes receiving a start address of the binary data vector and a power-of-2-stride elements of the data vector and determining offsets, wherein the offsets are determined by applying a plurality of bit-level XOR functions to the start address resulting in a Z vector, using the Z vector for accessing a mapping table, and shifting mapping table access results according to a power-of-2-stride of the binary data vector. Additionally, the method includes determining a sequence of portions of the binary data vector in the n memory banks depending on a binary equivalent value of the Z vector, and accessing the binary data vector in the n memory banks of the memory unit in parallel.

Abstract: Systems, apparatuses, and methods for implementing flexible dictionary sharing techniques for caches are disclosed. A set-associative cache includes a dictionary for each data array set. When a cache line is to be allocated in the cache, a cache controller determines to which set a base index of the cache line address maps. Then, a selector unit determines which dictionary of a group of dictionaries stored by those sets neighboring this set would achieve the most compression for the cache line. This dictionary is then selected to compress the cache line. An offset is added to the base index of the cache line to generate a full index in order to map the cache line to the set corresponding to this chosen dictionary. The compressed cache line is stored in this set with the chosen dictionary, and the offset is stored in the corresponding tag array entry.

Abstract: The present disclosure includes apparatuses and methods related to scatter/gather in a memory device. An example apparatus comprises a memory device that includes an array of memory cells, sensing circuitry, and a memory controller coupled to one another. The sensing circuitry includes a sense amplifier and a compute component configured to implement logical operations. A channel controller is configured to receive a block of instructions, the block of instructions including individual instructions for at least one of a gather operation and a scatter operation. The channel controller is configured to send individual instructions to the memory device and to control the memory controller such that the at least one of the gather operation and the scatter operation is executed on the memory device based on a corresponding one of the individual instructions.

Abstract: An approach is provided in which a storage system detects that an extent residing on a first one of a set of physical storage devices requires relocation. The storage system identifies a set of backend connection properties of each of a set of backend connections between the storage system and the set of physical storage devices. The set of backend connection properties includes at least a connection bandwidth between the storage system and at least one of the physical storage devices. In turn, the storage system relocates the extent from the first physical storage device to a second one of the set of physical storage devices based at least in part, on the set of backend connection properties.

Abstract: An approach is provided in which a storage system detects that an extent residing on a first one of a set of physical storage devices requires relocation. The storage system identifies a set of backend connection properties of each of a set of backend connections between the storage system and the set of physical storage devices. The set of backend connection properties includes at least a connection bandwidth between the storage system and at least one of the physical storage devices. In turn, the storage system relocates the extent from the first physical storage device to a second one of the set of physical storage devices based at least in part, on the set of backend connection properties.

Abstract: Provided are a rewriting system capable of shortening rewrite time, a rewriting system and a computer used for the rewriting system. The rewriting system includes an ECU and a rewriting device for at least transmitting to the ECU a rewrite data of memory contents stored in a flash ROM 14B (memory), the flash ROM 14B (memory) includes a rewrite target area A2 in which the memory contents to be rewritten are stored and a non-rewrite target area A1 in which the memory contents not to be rewritten are stored, and the rewriting device transmits the rewrite data of the memory contents to the ECU only for the memory contents of the rewrite target area in the flash ROM 14B (memory).

Abstract: A system includes a storage volume configured to store a data set in a plurality of data blocks, a data store configured to store a plurality of captures of the data set in a plurality of data chunks, and file retrieval logic. The data set includes a file stored in a data block of the plurality of data blocks. The plurality of captures includes the file captured at different points in time. The file retrieval logic is configured to identify the plurality of data chunks in which the data block as captured in the plurality of captures is stored in the data store, retrieve the plurality of data chunks from the data store, and read the data block as captured in the plurality of captures from the plurality of data chunks to produce a plurality of file versions.

Abstract: A memory controller circuit is disclosed which is coupleable to a first memory circuit, such as DRAM, and includes: a first memory control circuit to read from or write to the first memory circuit; a second memory circuit, such as SRAM; a second memory control circuit adapted to read from the second memory circuit in response to a read request when the requested data is stored in the second memory circuit, and otherwise to transfer the read request to the first memory control circuit; predetermined atomic operations circuitry; and programmable atomic operations circuitry adapted to perform at least one programmable atomic operation. The second memory control circuit also transfers a received programmable atomic operation request to the programmable atomic operations circuitry and sets a hazard bit for a cache line of the second memory circuit.

Abstract: A storage system and method for thin provisioning are provided. In one embodiment, a storage system is provided comprising a memory and a controller. The controller is configured to provide a logical exported capacity of the memory to a host, wherein the logical exported capacity is greater than an actual storage capacity of the memory; receive a command from the host to write data to a logical address; determine whether there is available actual storage capacity in the memory to write the data; and write the data to a physical address in memory that corresponds to the logical address only if it is determined that there is available actual storage capacity in the memory to write the data. Other embodiments are possible, and each of the embodiments can be used alone or together in combination.

Abstract: A method for execution by a container instance manager (CIM) includes determining to create a new instance of a first data container, where the first data container is stored in a first memory location. Creation of the new instance of the first data container for storage in a second memory location is facilitated in response to the determining to create the new instance. The method further includes determining to remove a duplicate instance of a second data container. Deletion of the duplicate instance of the second data container from memory is facilitated in response to the determining to remove the duplicate instance.

Abstract: A device includes an address translation table to, in each node of a set of nodes in the address translation table, store a key value and a hash function identifier, a hash engine coupled with the address translation table to, for each node in the set of nodes, calculate a hash result for the key value by executing a hash function identified by the hash function identifier, and a processing unit coupled with the hash engine to, in response to a request to translate a virtual memory address to a physical memory address, identify a physical memory region corresponding to the virtual memory address based on the calculated hash result for each node in the set of nodes.

Abstract: Technologies are disclosed herein that allow for utilization of memory channel storage (“MCS”) devices in a computing system. The MCS device may be detected during a boot phase of the computing system, and the address data for the MCS device may be detected through repeated manipulation of a logical offset. The address data may then be stored for later use in memory allocation.

Abstract: Techniques are provided for adaptive look-ahead configuration for data prefetching based on request size and frequency. One method comprises performing the following steps: estimating an earning value for a particular portion based on an average size and frequency of past input/output requests for the particular portion; calculating a quota for the particular portion by normalizing the earning value for the particular portion of the storage system based on earning values of one or more additional portions of the storage system; obtaining a size of a look-ahead window for a new request based on the quota for the particular portion over a prefetch budget assigned to the storage system; and moving a requested data item and one or more additional data items within the look-ahead window from the storage system to the cache memory responsive to the requested data item and/or the additional data items within the look-ahead window not being in the cache memory.

Abstract: A multi-core processing device and an inter-core data transmission method thereof are disclosed, the multi-core processing device includes a plurality of cores; each core includes at least one level cache, and when any core as a target core or of a target core group receives a cache line deliver request instruction from another core as a source core, the any core pre-fetches a corresponding cache line from the source core to a cache of the any core; and the cache line deliver request instruction includes an identifier hint of the target core.

Abstract: The subject technology provides for recovering a validity table for a data storage system. A set of logical addresses in a mapping table is partitioned into subsets of logical addresses. Each of the subsets of logical addresses is assigned to respective processor cores in the data storage system. Each of the processor cores is configured to check each logical address of the assigned subset of logical addresses in the mapping table for a valid physical address mapped to the logical address, for each valid physical address mapped to a logical address of the assigned subset of logical addresses, increment a validity count in a local validity table associated with a blockset of the non-volatile memory corresponding to the valid physical address, and update validity counts in a global validity table associated with respective blocksets of the non-volatile memory with the validity counts in the local validity table.

Abstract: A dual-server based storage system maintains a first cache and a first non-volatile storage (NVS) in a first server, and a second cache and a second NVS in a second server, where data in the first cache is also written in the second NVS and data in the second cache is also written in the first NVS. In response to a failure of the first server, a determination is made as to whether space exists in the second NVS to accommodate the data stored in the second cache. In response to determining that space exists in the second NVS to accommodate the data stored in the second cache, the data is transferred from the second cache to the second NVS.

Abstract: One embodiment is related to a method for applying deduplication and/or compression to data stored or to be stored at a non-volatile memory (NVM) cache comprising: identifying the NVM cache; determining whether deduplication or compression, or both, is to be applied to data stored or to be stored at the NVM cache; and applying either deduplication or compression, or both, to the data stored or to be stored at the NVM cache.

Abstract: A method that receives, at a first compute server of a plurality of compute servers, a request from a client device, wherein the request is a request for a network resource. The method locates at least one content item in response to the request for the network resource, detects possible dynamic content in the at least one content item, compares a first dynamic value in a first copy of the at least one content item to a second dynamic value in a second copy of the at least one content item from an origin server, and stores the at least one content item in a local cache as a safe content item to be returned for subsequent requests of the at least one content item in response to the first dynamic value matching the second dynamic value.

Abstract: Techniques for processing I/O operations may include: randomly assigning extent identifiers of extents to RAID groups; receiving write activity information for the extents for a sampling period; for each of the RAID groups, performing stream detection processing in accordance with the first write activity information and determining stream groups, wherein each stream group of one of the RAID groups includes extents of the RAID group belonging to a same write stream in the RAID group, wherein stream groups across all RAID groups are uniquely identified using stream group identifiers; tagging a write operation directed to one of the extents with a first stream group identifier denoting a stream group including the one extent; and issuing the write operation to a solid state drive of one of the RAID groups. Stream detection may use K-Means clustering algorithm. An aggregate address range of logical devices is mapped to the extent identifiers.

Abstract: A computer device reads an indicator from a configuration file that identifies a granularity of units of data at which to track validity. The granularity is one of a plurality of granularities ranging from one unit of data to many units of data. The computer device generates a machine-readable file configured to cause a processing device of a memory system to track validity at the identified granularity using a plurality of data validity counters with each data validity counter in the plurality of data validity counters tracking validity of a group of units of data at the identified granularity. The computer device transfers the machine-readable file to a memory of the memory system.