Patents Examined by Michael T. Tran
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Patent number: 11651817Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array, a data storage circuit and a control circuit. The data storage circuit holds first data to be written into the memory cell and holds 1 bit data calculated from the first data. The control circuit writes the data of n bits into the memory cell in a first write operation and then executes a second write operation. The control circuit carries out the following control in the second write operation. It reads data stored in the memory cell in the first write operation. It restores the first data based on the data read from the memory cell and the 1 bit data held in the data storage circuit. It writes the restored first data into the memory cell.Type: GrantFiled: July 16, 2021Date of Patent: May 16, 2023Assignee: Kioxia CorporationInventor: Noboru Shibata
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Patent number: 11637237Abstract: This spin current magnetization rotational type magnetoresistive element includes a magnetoresistive effect element having a first ferromagnetic metal layer having a fixed magnetization orientation, a second ferromagnetic metal layer having a variable magnetization orientation, and a non-magnetic layer sandwiched between the first ferromagnetic metal layer and the second ferromagnetic metal layer, and spin-orbit torque wiring which extends in a direction that intersects the stacking direction of the magnetoresistive effect element, and is connected to the second ferromagnetic metal layer, wherein the electric current that flows through the magnetoresistive effect element and the electric current that flows through the spin-orbit torque wiring merge or are distributed in the portion where the magnetoresistive effect element and the spin-orbit torque wiring are connected.Type: GrantFiled: April 7, 2022Date of Patent: April 25, 2023Assignee: TDK CORPORATIONInventor: Tomoyuki Sasaki
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Patent number: 11631465Abstract: A non-volatile memory device includes an upper semiconductor layer including a first metal pad and vertically stacked on a lower semiconductor layer. The upper semiconductor layer includes a first memory group spaced apart from a second memory group in a first horizontal direction by a separation region, and the lower semiconductor layer includes a second metal and a bypass circuit underlying at least a portion of the separation region and configured to selectively connect a first bit line of the first memory group with a second bit line of the second memory group. The upper semiconductor layer is vertically connected to the lower semiconductor layer by the first metal pad and the second metal pad.Type: GrantFiled: October 6, 2021Date of Patent: April 18, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Youn-Yeol Lee, Wook-Ghee Hahn
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Patent number: 11631445Abstract: A semiconductor apparatus includes a memory controller and data storage configured to input and output data in synchronization with a clock signal provided from the memory controller. The data storage includes a memory cell array and a data output apparatus configure to output read data from the memory cell array by sensing a logic level of the read data during a low-level period of a first clock, which is an inverted signal of a divided clock of the clock signal, and a low-level period of a second clock, the second clock having a set to phase delay amount from the divided clock.Type: GrantFiled: June 7, 2021Date of Patent: April 18, 2023Assignee: SK hynix Inc.Inventor: Eun Ji Choi
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Patent number: 11626153Abstract: A low power SRAM (static RAM) for an image sensor includes a voltage generation circuit for providing a positive supply voltage VP and a negative supply VN, wherein VDD>Vp>Vn>Vgnd; a plurality of memory cells coupled to a respective plurality of column sense lines in a pixel array, the plurality of memory cells receiving differential inputs dp and dn; and a Gray counter coupled to switchably couple VP and VN to the differential inputs dp and dn of the plurality of memory cells. A method of operating an image sensor with a low power SRAM includes acquiring an image by the image sensor; generating VP and VN such that VDD>VP>VN>Vgnd; receiving an output g of a column of pixels at a clock input of a memory cell; and switchably coupling VP and VN to the differential inputs dp and dn of a plurality of memory cells in the SRAM according to a codeword from a Gray counter.Type: GrantFiled: June 7, 2021Date of Patent: April 11, 2023Assignee: OmniVision Technologies, Inc.Inventor: Robert Johansson
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Patent number: 11625182Abstract: The storage device includes a memory controller and a plurality of banks, each of the plurality of banks including a plurality of memory devices. Each of the plurality of memory devices includes: a data selector for selecting and outputting data of a memory device that is included in any one of the plurality of banks based on a bank select signal; a latch unit for storing the data that is output from the data selector; and a transmission control signal generator for generating the bank select signal such that the data that is stored in the latch unit is sequentially output.Type: GrantFiled: March 5, 2021Date of Patent: April 11, 2023Assignee: SK hynix Inc.Inventor: Wan Seob Lee
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Patent number: 11620216Abstract: Disclosed in some examples are memory devices which feature intelligent adjustments to SLC cache configurations that balances memory cell lifetime with performance. The size of the SLC cache can be adjusted during usage of the memory device based upon a write amplification (WA) metric of the memory device. In some examples, the size of the SLC cache can be adjusted during usage of the memory device based upon a write amplification (WA) metric of the memory device and a memory device logical saturation metric (percentage of valid user data written in the device of the total user size).Type: GrantFiled: May 23, 2022Date of Patent: April 4, 2023Assignee: Micron Technology, Inc.Inventors: Xinghui Duan, Guanzhong Wang, Xu Zhang, Eric Kwok Fung Yuen
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Patent number: 11615859Abstract: An OTP with ultra-low power read can be programmed with a minimum and a maximum program voltage. When programming within the range, the post-program OTP to pre-program resistance ratio can be larger than N, where N>50, so that more sensing techniques, such as single-end sensing, can be used to reduce read current. At least one of the OTP cells can be coupled to a common bitline, which can be further coupled to a first supply voltage lines via a plurality of datalines. The resistance in the at least one OTP cell can be evaluated by strobing at least one comparator output of the discharging bitline/dataline.Type: GrantFiled: July 12, 2021Date of Patent: March 28, 2023Assignee: Attopsemi Technology Co., LTDInventor: Shine C. Chung
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Patent number: 11615849Abstract: A method for programming a memory device including a first plane and a second plane is provided. The method includes simultaneously initiating programming of the first plane and the second plane, and in response to the first plane being successfully programmed and the second plane not being successfully programmed, suspending the programming of the first plane, and keeping the programming of the second plane.Type: GrantFiled: August 27, 2021Date of Patent: March 28, 2023Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Haibo Li, Chao Zhang
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Patent number: 11610617Abstract: A magnetic memory according to an embodiment includes: a first wiring and a second wiring; a first magnetic member having a first portion electrically connected to the first wiring and a second portion electrically connected to the second wiring, the first magnetic member extending in a first direction from the first portion to the second portion; a third wiring that is electrically insulated from the first magnetic member; and a control circuit electrically connected to the first wiring, the second wiring, and the third wiring, the control circuit supplying a current pulse, in which a trailing time is longer than a rising time, to the third wiring.Type: GrantFiled: June 16, 2021Date of Patent: March 21, 2023Assignee: Kioxia CorporationInventors: Naoharu Shimomura, Michael Arnaud Quinsat, Masahiro Koike
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Patent number: 11610942Abstract: Technologies relating to crossbar array circuits with parallel grounding lines are disclosed. An example crossbar array circuit includes: a word line; a bit line; a first selector line, a grounding line; a first transistor including a first source terminal, a first drain terminal, a first gate terminal, and a first body terminal; and an RRAM device connected in series with the first transistor. The grounding line is connected to the first body terminal and is grounded and the grounding line parallel to the bit line. The first selector line is connected to the first gate terminal. In some implementations, the RRAM device is connected between the first transistor via the first drain terminal and the word line, and the first source terminal is connected to the bit line.Type: GrantFiled: June 24, 2021Date of Patent: March 21, 2023Assignee: TetraMem Inc.Inventor: Ning Ge
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Patent number: 11610639Abstract: A reading method for a non-volatile memory device, includes performing a normal read operation using a default read level in response to a first read command; and performing a read operation using a multiple on-chip valley search (OVS) sensing operation in response to a second read command, when read data read in the normal read operation are uncorrectable.Type: GrantFiled: June 2, 2021Date of Patent: March 21, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Eunhyang Park, Jinyoung Kim, Jisang Lee, Sehwan Park, Ilhan Park
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Patent number: 11611037Abstract: This spin current magnetization rotational type magnetoresistive element includes a magnetoresistive effect element having a first ferromagnetic metal layer having a fixed magnetization orientation, a second ferromagnetic metal layer having a variable magnetization orientation, and a non-magnetic layer sandwiched between the first ferromagnetic metal layer and the second ferromagnetic metal layer, and spin-orbit torque wiring which extends in a direction that intersects the stacking direction of the magnetoresistive effect element, and is connected to the second ferromagnetic metal layer, wherein the electric current that flows through the magnetoresistive effect element and the electric current that flows through the spin-orbit torque wiring merge or are distributed in the portion where the magnetoresistive effect element and the spin-orbit torque wiring are connected.Type: GrantFiled: April 7, 2022Date of Patent: March 21, 2023Assignee: TDK CORPORATIONInventor: Tomoyuki Sasaki
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Patent number: 11599458Abstract: According to some example embodiments of the inventive concepts, there is provided a method of operating a stacked memory device including a plurality of memory dies stacked in a vertical direction, the method including receiving a command and an address from a memory controller, determining a stack ID indicating a subset of the plurality of memory dies by decoding the address, and accessing at least two memory dies among the subset of memory dies corresponding to the stack ID such that the at least two memory dies are non-adjacent.Type: GrantFiled: December 15, 2021Date of Patent: March 7, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Joonsik Sohn, Hyunjoong Kim, Woongjae Song, Soowoong Ahn, Seunghyun Cho, Jihyun Choi
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Patent number: 11599299Abstract: Some embodiments provide a three-dimensional (3D) circuit that has data lines of one or more memory circuits on a different IC die than the IC die(s) on which the memory blocks of the memory circuit(s) are defined. In some embodiments, the 3D circuit includes a first IC die with a first set of two or more memory blocks that have a first set of data lines. The 3D circuit also includes a second IC die that is stacked with the first IC dies and that includes a second set of two or more memory blocks with a second set of data lines. The 3D circuit further includes a third IC die that is stacked with the first and second IC dies and that includes a third set of data lines, which connect through several z-axis connections with the first and second sets of data lines to carry data to and from the first and second memory block sets when data is being written to and read from the first and second memory block sets.Type: GrantFiled: November 13, 2020Date of Patent: March 7, 2023Assignee: Invensas LLCInventors: Javier A. DeLaCruz, David E. Fisch
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Patent number: 11588107Abstract: An IC structure comprises a substrate, a first material layer, a second material layer, a first via structure, and a memory cell structure. The substrate comprises a memory region and a logic region. The first material layer is disposed on the memory region and the logic region. The second material layer is disposed on the first material layer only at the memory region. The first via structure formed in the first material layer and the second material layer. The memory cell structure is over the first via structure.Type: GrantFiled: July 7, 2021Date of Patent: February 21, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tai-Yen Peng, Hui-Hsien Wei, Wei-Chih Wen, Pin-Ren Dai, Chien-Min Lee, Han-Ting Tsai, Jyu-Horng Shieh, Chung-Te Lin
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Patent number: 11588104Abstract: Embodiments of the present invention include a memory cell that has a vertically-oriented fin. The memory cell may also include a resistive memory device located on a first lateral side of the fin. The resistive memory device may include a bottom electrode, a top electrode, and a resistive element between the bottom electrode and the top electrode. The memory cell may also include a vertical field-effect transistor having a metal gate and a gate dielectric contacting a second lateral side of the fin opposite the first lateral side.Type: GrantFiled: June 14, 2021Date of Patent: February 21, 2023Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Carl Radens, Ruilong Xie, Juntao Li
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Patent number: 11587641Abstract: A fuse fault repair circuit includes a fuse array, a signal storage module, and a scan repair module. The fuse array includes a redundant fuse array and a non-redundant fuse array. When the fuse array is not faulty, the redundant fuse array has no signal output, and the non-redundant fuse array outputs S first logic signals. Each storage unit in the signal storage module is configured to store a first logic signal sent by one fuse unit connected thereto. The scan repair module is configured to scan the storage units in the signal storage module, determine, when a faulty storage unit is scanned, that a first fuse unit connected to the faulty storage unit is faulty, and replace the first fuse unit with a first redundant fuse unit corresponding to the first fuse unit. The first logic signal corresponding to the first redundant fuse unit is a normal signal.Type: GrantFiled: October 11, 2021Date of Patent: February 21, 2023Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.Inventor: Kejun Wang
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Patent number: 11587623Abstract: A content-address memory (CAM) and an operation method are provided. The content-address memory comprises: a plurality of first signal lines; a plurality of second signal lines; and a plurality of CAM memory cells coupled to the first signal lines and the second signal lines, wherein in data match, a plurality of input signals are input into the CAM memory cells via the first signal lines; the input signals are compared with contents stored in the CAM memory cells; and a match result is determined based on an electrical characteristic of the second signal lines.Type: GrantFiled: May 14, 2021Date of Patent: February 21, 2023Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Po-Hao Tseng, Yu-Hsuan Lin, Feng-Min Lee, Ming-Hsiu Lee
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Patent number: 11581049Abstract: Apparatus and methods are described to reduce program disturb for a memory string with a partial select gate drain, which is partially cut by a shallow trench. The memory string with a partial select gate drain is linked with a neighboring full select gate drain that during its programming can cause a program disturb in the memory string with a partial select gate drain. The bias voltage applied to the selected full select gate drain can be controlled from a high state for low memory program states to a lower state for the high memory program states. The high data states may cause program disturb. The reduction in the bias voltage can match a reduction in the bias voltage applied to the bit lines to reduce the program disturb while providing adequate signal to program the high states on the memory string of the full select gate drain.Type: GrantFiled: June 1, 2021Date of Patent: February 14, 2023Assignee: SanDisk Technologies LLCInventors: Kazuki Isozumi, Parth Amin, Sayako Nagamine, Anubhav Khandelwal
