Patents Examined by Michael T. Tran
  • Content-addressable memory and operation method thereof
    Patent number: 11587623
    Abstract: A content-address memory (CAM) and an operation method are provided. The content-address memory comprises: a plurality of first signal lines; a plurality of second signal lines; and a plurality of CAM memory cells coupled to the first signal lines and the second signal lines, wherein in data match, a plurality of input signals are input into the CAM memory cells via the first signal lines; the input signals are compared with contents stored in the CAM memory cells; and a match result is determined based on an electrical characteristic of the second signal lines.
    Type: Grant
    Filed: May 14, 2021
    Date of Patent: February 21, 2023
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Po-Hao Tseng, Yu-Hsuan Lin, Feng-Min Lee, Ming-Hsiu Lee
  • System and methods for programming nonvolatile memory having partial select gate drains
    Patent number: 11581049
    Abstract: Apparatus and methods are described to reduce program disturb for a memory string with a partial select gate drain, which is partially cut by a shallow trench. The memory string with a partial select gate drain is linked with a neighboring full select gate drain that during its programming can cause a program disturb in the memory string with a partial select gate drain. The bias voltage applied to the selected full select gate drain can be controlled from a high state for low memory program states to a lower state for the high memory program states. The high data states may cause program disturb. The reduction in the bias voltage can match a reduction in the bias voltage applied to the bit lines to reduce the program disturb while providing adequate signal to program the high states on the memory string of the full select gate drain.
    Type: Grant
    Filed: June 1, 2021
    Date of Patent: February 14, 2023
    Assignee: SanDisk Technologies LLC
    Inventors: Kazuki Isozumi, Parth Amin, Sayako Nagamine, Anubhav Khandelwal
  • Memory sub-system refresh
    Patent number: 11579797
    Abstract: A method includes determining a first memory access count threshold for a first word line of a block of memory cells and determining a second memory access count threshold for a second word line of the block of memory cells. The second memory access count threshold can be greater than the first memory access count threshold. The method can further include incrementing a memory block access count corresponding to the block of memory cells that includes the first word line and the second word line in response to receiving a memory access command and refreshing the first word line when the memory block access count corresponding to the block of memory cells is equal to the first memory access count threshold.
    Type: Grant
    Filed: April 29, 2021
    Date of Patent: February 14, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Tao Liu, Ting Luo, Jianmin Huang
  • Improper ferroelectric active and passive devices
    Patent number: 11581417
    Abstract: A capacitor is provided which comprises: a first structure comprising metal; a second structure comprising metal; and a third structure between the first and second structures, wherein the third structure comprises an improper ferroelectric material. In some embodiments, a field effect transistor (FET) is provided which comprises: a substrate; a source and drain adjacent to the substrate; and a gate stack between the source and drain, wherein the gate stack includes: a dielectric; a first structure comprising improper ferroelectric material, wherein the first structure is adjacent to the dielectric; and a second structure comprising metal, wherein the second structure is adjacent to the first structure.
    Type: Grant
    Filed: September 13, 2018
    Date of Patent: February 14, 2023
    Assignee: Intel Corporation
    Inventors: Sasikanth Manipatruni, Uygar Avci, Sou-Chi Chang, Ian Young
  • Nonconsecutive mapping scheme for data path circuitry in a storage device
    Patent number: 11573914
    Abstract: A data storage system includes a storage medium including a plurality of columns of memory cells, a storage controller coupled to the storage medium, and data path circuitry including a data bus coupled to the storage controller, the data bus configured to receive a plurality of bytes of data to be written to the plurality of columns of memory cells; a block of data latches having a pitch equal to a first number of bit lines of the plurality of columns of memory cells; and column redundancy circuitry configured to pass the plurality of bytes of data to the block of data latches via the plurality of columns in accordance with a nonconsecutive mapping scheme. The nonconsecutive mapping scheme includes mapping each group of three bytes to two columns by splitting one byte of each group of three bytes into two nibbles.
    Type: Grant
    Filed: March 19, 2021
    Date of Patent: February 7, 2023
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Hiroki Yabe, Masahito Takehara
  • Three-dimensional memory array
    Patent number: 11574957
    Abstract: An example three-dimensional (3-D) memory array includes a first plurality of conductive lines separated from one other by an insulation material, a second plurality of conductive lines, and a plurality of pairs of conductive pillars arranged to extend substantially perpendicular to the first plurality of conductive lines and the second plurality of conductive lines. The conductive pillars of each respective pair are coupled to a same conductive line of the second plurality of conductive lines. A storage element material is formed partially around the conductive pillars of each respective pair.
    Type: Grant
    Filed: May 14, 2021
    Date of Patent: February 7, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Anna Maria Conti, Andrea Redaelli, Agostino Pirovano
  • Electronic device
    Patent number: 11568928
    Abstract: A semiconductor memory includes a substrate including a cell region, a first peripheral circuit region, and a second peripheral circuit region; a plurality of first lines disposed over the substrate across the cell region and the first peripheral circuit region; a plurality of second lines disposed over the first lines across the cell region and the second peripheral circuit region; and a first memory cell positioned at each of intersections between the first lines and the second lines, wherein the cell region includes a first cell region and a second cell region, the first cell region being disposed closer to the first and second peripheral circuit regions than the second cell region, and wherein a first portion of the second line that is in the first cell region has a greater resistance than a second portion of the second line that is in the second cell region.
    Type: Grant
    Filed: April 1, 2021
    Date of Patent: January 31, 2023
    Assignee: SK hynix Inc.
    Inventor: Hwang Yeon Kim
  • Three-dimensional confined memory cell with decoupled read-write
    Patent number: 11569444
    Abstract: An embodiment of the invention may include a first electrode, a second electrode, and a multi-level nonvolatile electrochemical cell located between the first electrode and second electrode. The multi-level nonvolatile electrochemical cell may have a read path and a write path through the cell, where the read path and the write path are different.
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: January 31, 2023
    Assignee: International Business Machines Corporation
    Inventor: John Rozen
  • Two-terminal non-volatile memory cell for decoupled read and write operations
    Patent number: 11568927
    Abstract: An embodiment of the invention may include a memory structure. The memory structure may include a first terminal connected to a first contact. The memory structure may include a second terminal connected to a second contact and a third contact. The memory structure may include a multi-level nonvolatile electrochemical cell having a variable resistance channel and a programming gate. The memory structure may include the first contact and second contact connected to the variable resistance channel. The memory structure may include the third contact is connected to the programming gate. This may enable decoupled read-write operations of the device.
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: January 31, 2023
    Assignee: International Business Machines Corporation
    Inventors: John Rozen, Seyoung Kim, Paul Michael Solomon
  • High-reliability magnetic memory system and method of operating the same
    Patent number: 11568911
    Abstract: Provided is a method of operating a magnetic memory system. The method of operating the magnetic memory system includes: preparing a plurality of magnetic memory cells; classifying the magnetic memory cells into a plurality of magnetic memory cell groups by using program current values of the magnetic memory cells; constructing a magnetic memory system by hierarchizing the magnetic memory cell groups; and primarily performing programming by selecting one magnetic memory cell group from the hierarchized magnetic memory cell groups according to an external temperature.
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: January 31, 2023
    Assignee: IUCF-HYU (INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY)
    Inventors: Taewhan Kim, Woo Seong Chung
  • Speculative section selection within a memory device
    Patent number: 11562805
    Abstract: Methods, systems, and devices for speculative memory section selection are described. Defective memory components in one memory section may be repaired using repair components in another memory section. Speculative selection of memory sections may be enabled, whereby access lines in multiple memory sections may be selected when a memory command indicating an address in one memory section is received. While the access lines in the multiple memory sections are selected, a determination of whether repair components in another memory section are to be accessed is performed. Based on the determination, the access line in one of the memory sections may be maintained and the access lines in the other memory sections may be deselected.
    Type: Grant
    Filed: November 13, 2020
    Date of Patent: January 24, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Richard E. Fackenthal, Jahanshir Javanifard, Duane R. Mills
  • Memory device
    Patent number: 11557329
    Abstract: A memory device includes a first substrate, a first memory array, a second substrate, and at least one first vertical transistor. The first memory array is disposed on the first substrate. The first memory array includes at least one first word line structure. The first memory array is disposed between the first substrate and the second substrate in a vertical direction. The first vertical transistor is electrically connected with the first word line structure. At least a part of the at least one first vertical transistor is disposed in the second substrate.
    Type: Grant
    Filed: June 1, 2020
    Date of Patent: January 17, 2023
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: Qiang Tang, Chunyuan Hou
  • Weyl semimetal material for magnetic tunnel junction
    Patent number: 11552242
    Abstract: In some examples, a device includes a magnetic tunnel junction including a first Weyl semimetal layer, a second Weyl semimetal layer, and a dielectric layer positioned between the first and second Weyl semimetal layers. The magnetic tunnel junction may have a large tunnel magnetoresistance ratio, which may be greater than five hundred percent or even greater than one thousand percent.
    Type: Grant
    Filed: April 8, 2021
    Date of Patent: January 10, 2023
    Assignee: Regents of the University of Minnesota
    Inventors: Duarte José Pereira de Sousa, Cesar Octavio Ascencio, Jian-Ping Wang, Tony Low
  • Probabilistic data integrity scan with dynamic scan frequency
    Patent number: 11545229
    Abstract: Exemplary methods, apparatuses, and systems include receiving a plurality of read operations. The read operations are divided into a current set of a sequence of read operations and one or more other sets. The size of the current set is a first number of read operations. An aggressor read operation is selected from the current set. A first data integrity scan is performed on a victim of the aggressor and a first indicator of data integrity is determined based on the first data integrity scan. In response to determining the first indicator of data integrity is greater than a current maximum value, the current maximum value is set to the first indicator of data integrity. In response to determining the current maximum value satisfies a threshold value, a size of a subsequent set of read operations is set to a second number, which less than the first number.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: January 3, 2023
    Assignee: MICRON TECHNOLOGY, INC.
    Inventor: Saeed Sharifi Tehrani
  • Split-gate memory cells
    Patent number: 11545220
    Abstract: Memory might include an array of memory cells having a plurality of strings of series-connected split-gate memory cells each including a primary memory cell portion and an assist memory cell portion, a plurality of primary access lines each connected to a control gate of the primary memory cell portion of a respective split-gate memory cell of each string of series-connected split-gate memory cells of the plurality of strings of series-connected split-gate memory cells, and a plurality of assist access lines each connected to a control gate of the assist memory cell portion of its respective split-gate memory cell of each string of series-connected split-gate memory cells of the plurality of strings of series-connected split-gate memory cells.
    Type: Grant
    Filed: June 18, 2021
    Date of Patent: January 3, 2023
    Assignee: Micron Technology, Inc.
    Inventor: Tomoharu Tanaka
  • Nonvolatile memory device and operating method of the same
    Patent number: 11545224
    Abstract: A nonvolatile memory device and an operating method thereof are provided. The nonvolatile memory device includes a memory cell array including first to third memory cells sequentially arranged in a vertical stack structure and a control logic configured to apply a first non-selection voltage to the first memory cell, apply a second non-selection voltage different from the first non-selection voltage to the third memory cell, apply a selection voltage to the second memory cell, and select the second memory cell as a selection memory cell.
    Type: Grant
    Filed: May 3, 2021
    Date of Patent: January 3, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yumin Kim, Seyun Kim, Jinhong Kim, Soichiro Mizusaki, Youngjin Cho
  • Power savings mode toggling to prevent bias temperature instability
    Patent number: 11545209
    Abstract: Systems and methods for injecting a toggling signal in a command pipeline configured to receive a multiple command types for the memory device. Toggling circuitry is configured to inject the toggling signal into at least a portion of the command pipeline when the memory device is in a power saving mode and the command pipeline is clear of valid commands. The toggling is blocked from causing writes by disabling a data strobe when a command that is invalid in the power saving mode is asserted during the power saving mode.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: January 3, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Parthasarathy Gajapathy, Kallol Mazumder
  • Memory device, method of forming the same, and memory array
    Patent number: 11538858
    Abstract: Provided are a memory device and a method of forming the same. The memory device includes: a selector; a magnetic tunnel junction (MTJ) structure, disposed on the selector; a spin orbit torque (SOT) layer, disposed between the selector and the MTJ structure, wherein the SOT layer has a sidewall aligned with a sidewall of the selector; a transistor, wherein the transistor has a drain electrically coupled to the MTJ structure; a word line, electrically coupled to a gate of the transistor; a bit line, electrically coupled to the SOT layer; a first source line, electrically coupled to a source of the transistor; and a second source line, electrically coupled to the selector, wherein the transistor is configured to control a write signal flowing between the bit line and the second source line, and control a read signal flowing between the bit line and the first source line.
    Type: Grant
    Filed: June 29, 2021
    Date of Patent: December 27, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Min Lee, Ming-Yuan Song, Yen-Lin Huang, Shy-Jay Lin, Tung-Ying Lee, Xinyu Bao
  • Controller and operation method thereof
    Patent number: 11532364
    Abstract: A controller for controlling a memory device including memory cells, the controller includes: a memory suitable for storing offset level information which is determined based on a sample read level according to characteristics of the memory cells and Gaussian modeling of the memory cells; and a processor suitable for generating an estimated read level based on the Gaussian madding and data read from the memory cells, and applying a compensated read voltage to control the memory device to perform read operations of the memory cells, wherein the compensated read voltage is generated by applying the offset level information to the estimated read level.
    Type: Grant
    Filed: April 26, 2021
    Date of Patent: December 20, 2022
    Assignee: SK hynix Inc.
    Inventor: Dae Sung Kim
  • Storage device, electronic component, and electronic device
    Patent number: 11532340
    Abstract: A novel storage device is provided. The storage device includes a first wiring, a second wiring, and a first memory cell. The first memory cell includes a first transistor and a first magnetic tunnel junction device. One of a source or a drain of the first transistor is electrically connected to a first wiring. The other of the source or the drain of the first transistor is electrically connected to one terminal of the first magnetic tunnel junction device. Another terminal of the first magnetic tunnel junction device is electrically connected to the second wiring. The first transistor includes an oxide semiconductor in its channel formation region.
    Type: Grant
    Filed: May 21, 2021
    Date of Patent: December 20, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yoshiaki Oikawa, Atsushi Miyaguchi, Hideki Uochi