Abstract: In a method of forming a semiconductor device, a plurality of transistor pairs is formed to be stacked over a substrate. The plurality of transistor pairs have a plurality of gate electrodes that are stacked over the substrate and electrically coupled to gate structures of the plurality of transistor pairs, and a plurality of source/drain (S/D) local interconnects that are stacked over the substrate and electrically coupled to source regions and drain regions of the plurality of transistor pairs. A sequence of vertical and lateral etch steps are performed to etch the plurality of the gate electrodes and the plurality of S/D local interconnects so that the plurality of the gate electrodes and the plurality of S/D local interconnects have a staircase configuration.

Abstract: A semiconductor device includes a field effect transistor (FET). The FET includes a first channel, a first source and a first drain; a second channel, a second source and a second drain; and a gate structure disposed over the first and second channels. The gate structure includes a gate dielectric layer and a gate electrode layer. The first source includes a first crystal semiconductor layer and the second source includes a second crystal semiconductor layer. The first source and the second source are connected by an alloy layer made of one or more Group IV element and one or more transition metal elements. The first crystal semiconductor layer is not in direct contact with the second crystal semiconductor layer.

Abstract: A light emitting diode (LED) package structure include an electrically-insulated frame, a trough, a LED chip, a fluorescent colloid and at least two spacing members. The electrically-insulated frame has a surface with four corners. The trough is recessed in the surface. The LED chip is located in the trough. The fluorescent colloid is filled within the trough to cover the LED chip. The spacing members protrude from two of the four corners on the surface, wherein a glue escape gap is defined between each spacing member and a boundary of the trough.

Abstract: The present invention relates to a process for manufacturing an optoelectronic device, wherein a layer of a formulation containing a silazane polymer and a wavelength converting material is applied to an optoelectronic device precursor, precured by exposure to radiation and then cured. There is further provided an optoelectronic device, preferably a light emitting device (LED) or a micro-light emitting device (micro-LED), which is prepared by said manufacturing process.

Abstract: A display device may include a substrate. A first light emitting element is disposed on the substrate. A second light emitting element is disposed on the substrate and is positioned adjacent to the first light emitting element. A first encapsulation layer is disposed on the first light emitting element and the second light emitting element. A light path control layer is disposed on the first encapsulation layer. The light path control layer includes a first pattern overlapping the first light emitting element and having a first refractive index and a second pattern overlapping the second light emitting element and having a second refractive index that is greater than the first refractive index.

Abstract: A light emitting device includes: a light emitting element; a wavelength conversion member including: a wavelength conversion portion arranged on or above an upper surface of the light emitting element, and a light-transmissive portion, wherein, in a plan view, the light-transmissive portion surrounds at least one or more lateral surfaces of the wavelength conversion portion; a sealing member comprising a lens portion that is arranged on or above an upper surface of the wavelength conversion member; and a light reflection member that surrounds one or more lateral surfaces of the wavelength conversion member. In a plan view, the wavelength conversion member is inside a perimeter of the lens portion.

Abstract: A memory device includes a word line, a bit line, an active region and a bit line contact structure. The word line is disposed in the substrate, and extends along a first direction. The bit line is disposed over the substrate, and extends along a second direction. The active region is disposed in the substrate, and extends along a third direction. The bit line contact structure is disposed between the active region and the bit line. A top view pattern of the bit line contact structure has a long axis. An angle between the extending direction of this long axis and the third direction is less than an angle between the extending direction of this long axis and the first direction, and is less than an angle between the extending direction of this long axis and the second direction.

Abstract: A conductive gate over a semiconductor fin is cut into a first conductive gate and a second conductive gate. An oxide is removed from sidewalls of the first conductive gate and a dielectric material is applied to the sidewalls. Spacers adjacent to the conductive gate are removed to form voids, and the voids are capped with a dielectric material to form air spacers.

Abstract: A semiconductor device assembly includes a substrate and a die coupled to the substrate. The die includes a first contact pad electrically coupled to a first circuit on the die including at least one active circuit element, and a second contact pad electrically coupled to a second circuit on the die including only passive circuit elements. The substrate includes a substrate contact electrically coupled to both the first and second contact pads. The semiconductor device assembly can further include a second die including a third contact pad electrically coupled to a third circuit on the second die including at least a second active circuit element, and a fourth contact pad electrically coupled to a fourth circuit on the second die including only passive circuit elements. The substrate contact can be electrically coupled to the third contact pad and electrically disconnected from the fourth contact pad.

Abstract: The light emitting device includes: at least one light emitting element including a light-extracting surface and at least one lateral surface; a wavelength converting member including; a first upper surface and a second upper surface, a lower surface located at an opposite side from the first upper surface and the second upper surface, at least one first lateral surface connecting the second upper surface and the first upper surface, and at least one second lateral surface connecting the second upper surface and the lower surface, in which a thickness between the lower surface and the first upper surface is smaller than a thickness between the lower surface and the second upper surface, and the first upper surface is located at an opposite side from the light-extracting surface of a corresponding one of the at least one light emitting element, and the lower surface is located facing the light-extracting surface of the corresponding one of the at least one light emitting element; a covering member covering the

Abstract: A display device includes a substrate, a first light-emitting diode, an encapsulant and a first Fresnel lens. The first light emitting diode is located on the substrate. The encapsulant covers the first light emitting diode. The first Fresnel lens is located on the encapsulant and overlapping with the first light emitting diode. The width of the first Fresnel lens is 4 to 10 times the width of the first light emitting diode.

Abstract: A semiconductor structure includes: a first die, comprising a first interconnect structure and a first active pad electrically connected to the first interconnect structure; a first bonding dielectric layer over the first die; a first active bonding via in the first bonding dielectric layer, electrically connected to the first interconnect structure; and a plurality of first dummy bonding vias in the first bonding dielectric layer, wherein the first dummy bonding vias laterally surround the first active bonding via and are electrically floating.

Abstract: A structure and a method of forming are provided. A first work function layer is formed over a first fin and terminates closer to the first fin than an adjacent second fin. A second work function layer is formed over the first work function layer and terminates closer to the second fin than the adjacent second fin. A third work function layer is formed over the first work function layer and the second fin. A conductive layer is formed over the third work function layer.

Abstract: A display panel includes a substrate having a first area and a second area, a non-display area surrounding the first area and the second area, and a display area surrounding the non-display area, a plurality of display elements arranged in the display area, and a plurality of signal lines electrically connected to the plurality of display elements, wherein the plurality of signal lines includes a first signal line and a second signal line neighboring each other and extending in a first direction, wherein the first signal line bypasses in the non-display area along a first side of the first area, and the second signal line bypasses in the non-display area along a second side of the first area, and wherein the first and second signal lines are asymmetrical with respect to a virtual central line through a center of the first area in the first direction.

Abstract: A light emitting device includes a substrate, a plurality of first light emitting elements mounted on the substrate, including first LED dies, and emitting light having a first wavelength, and a light guide layer arranged so as to cover the plurality of first light emitting elements, and guiding the light from the plurality of first light emitting elements, wherein when LG1 is a distance between the first LED dies, and ?c is a critical angle of the light emitted from the light guide layer to the air, and a thickness T between the upper surfaces of the first light emitting elements and the upper surface of the light guide layer is equal to or longer than T1 indicated by T1=LG1/(2tan ?c).

Abstract: In this present invention lateral voltage variable capacitor designs are disclosed. The lateral voltage variable capacitor utilizes a dielectric material with an electric field dependent dielectric permittivity (dielectric constant). Variable capacitor structures are defined laterally in the plane of the substrate as opposed to vertical device structures defined out of the plane of the substrate.

Abstract: A micro semiconductor structure includes a substrate, a dissociative layer, a protective layer and a micro semiconductor. The dissociative layer is located on one side of the substrate. The protective layer is located on at least one side of the substrate. The micro semiconductor is located on the side of the substrate. The transmittance of the protective layer for a light source with wavelength smaller than 360 nm is less than 20%.

Abstract: A method of producing microelectronic components includes forming a functional layer system; applying a laminar carrier to the functional layer system; attaching a workpiece to a workpiece carrier; utilizing incident radiation of a laser beam is focused in a boundary region between a growth substrate and the functional layer system, and a bond between the growth substrate and the functional layer system in the boundary region is weakened or destroyed; separating a functional layer stack from the growth substrate, wherein a vacuum gripper having a sealing zone that circumferentially encloses an inner region is applied to the reverse side of the growth substrate, a negative pressure is generated in the inner region such that separation of the functional layer stack from the growth substrate is initiated in the inner region; and the growth substrate held on the vacuum gripper is removed from the functional layer stack.

Abstract: A method of fabricating a display device, the method comprising: preparing a mother substrate having a first cell region and a second cell region, and a first target region and a second target region in the first cell region and the second cell region, respectively; providing an encapsulation material on a first printing region in the first target region to form a first encapsulation layer; and providing the encapsulation material on a second printing region in the second target region to form a second encapsulation layer, wherein a center of the second printing region is shifted from a center of the second target region in a specific direction.

Abstract: A method of fabricating self-aligned grids in a BSI image sensor is provided. The method includes depositing a first dielectric layer over a back surface of a substrate that has a plurality of photodiodes formed therein, forming a grid of trenches, and filling in the trenches with dielectric material to create a trench isolation grid. Here, a trench passes through the first dielectric layer and extends into the substrate. The method further includes etching back dielectric material in the trenches to a level that is below an upper surface of the first dielectric layer to form recesses overlaying the trench isolation grid, and filling in the recesses with metallic material to create a metallic grid that is aligned with the trench isolation grid.