Abstract: The present application provides a laterally diffused metal oxide semiconductor (LDMOS) transistor and a manufacturing method thereof. The transistor comprising: a semiconductor substrate having a doping region, wherein the doping region comprises a first well region and a second well region with opposite doping types; a source region, a drain region, a shallow trench isolation (STI) structure comprising a laminated structure having an alternate layers of insulating material and ferroelectric material, a gate, a contact hole, and a metal layer. The LDMOS transistor simultaneously increases breakdown voltage (BV) and reduces on-resistance (Ron).

Abstract: A semiconductor structure is provided, and the semiconductor structure includes a substrate, and an active area is defined thereon, a gate structure spanning the active area, wherein the overlapping range of the gate structure and the active area is defined as an overlapping region, and the overlapping region includes four corners, and at least one salicide block covering the four corners of the overlapping region.

Abstract: A method of manufacturing a semiconductor light emitting device, the method including forming a first conductivity-type semiconductor layer on a substrate; forming an active layer on the first conductivity-type semiconductor layer; forming a mask layer having an opening on the active layer; growing a second conductivity-type semiconductor layer through the opening; removing the mask layer; removing a portion of the active layer and a portion of the first conductivity-type semiconductor layer that do not overlap the second conductivity-type semiconductor layer; and removing a portion of the first conductivity-type semiconductor layer to expose the substrate.

Abstract: A method for forming a semiconductor structure includes providing a substrate, including a first region and a second region; forming a plurality of fin structures on the substrate; forming an isolation structure between adjacent fin structures; forming a mask layer over the substrate and the plurality of fin structures; forming an opening by removing a portion of the mask layer formed in the first region; removing a portion of the isolation structure exposed in the opening by using a remaining portion of the mask layer as a mask; removing the remaining portion of the mask layer; and forming a gate structure across the plurality of fin structures. The gate structure covers the first region.

Abstract: A method of forming a vertical transport field effect transistor (VTFET) is provided. The method includes forming one or more vertical fins on a substrate, wherein there is a fin transition region between each of the one or more vertical fins and the substrate. The method further includes forming a sidewall liner having a first thickness on each of the one or more vertical fins. The method further includes forming a sidewall spacer having a second thickness on each of the sidewall liner(s), wherein the first thickness of the sidewall liner and the second thickness of the sidewall spacer determines an offset distance from each of the one or more vertical fins. The method further includes forming a trench with an edge offset from each of the one or more vertical fins by the offset distance.

Abstract: Disclosed in the present application are a quantum dot LED, a manufacturing method thereof, and a display device, belonging to the technical field of LED light sources. The quantum dot LED includes an LED support, an LED chip, a filling layer, and a quantum dot layer, where the LED support comprises a chamber; the LED chip is arranged on a bottom surface of the chamber; the filling layer covers the bottom surface of the chamber and the LED chip, and is engaged with walls of the chamber; and the quantum dot layer is arranged at an opening on a top surface of the chamber, a light incident side of the quantum dot layer abuts against a surface of the filling layer away from the bottom surface of the chamber, and a shortest distance h between the LED chip and the quantum dot layer meets h?0.03 mm.

Abstract: A semiconductor structure includes a first device and a second device. The first device includes: a first gate structure formed over an active region and a first air spacer disposed adjacent to the first gate structure. The second device includes: a second gate structure formed over an isolation structure and a second air spacer disposed adjacent to the second gate structure. The first air spacer and the second air spacer have different sizes.

Abstract: Disclosed herein are a white organic light-emitting device. The white organic light-emitting device enables an overall improvement in characteristics such as color temperature, efficiency, luminance, and service life, by changing the configuration of different types of emission layers in contact with each other, and a display device using the same.

Abstract: A semiconductor device having high on-state current and high reliability is provided. The semiconductor device includes, a first insulator; a first oxide over the first insulator; a second oxide over the first oxide; a first conductor and a second conductor over the second oxide; a third oxide over the second oxide; a second insulator over the third oxide; a third conductor located over the second insulator and overlapping with the third oxide; a third insulator in contact with a top surface of the first insulator, a side surface of the first oxide, a side surface of the second oxide, a side surface of the first conductor, a top surface of the first conductor, a side surface of the second conductor, and a top surface of the second conductor; a fourth insulator over the third insulator; a fifth insulator over the fourth insulator; and a sixth insulator over the third conductor, the second insulator, the third oxide and the fifth insulator.

Abstract: The present application discloses a display panel and method of manufacturing thereof. The display panel of the present application includes a substrate, an active switch, a color photoresist layer, a first electrode layer, a light emitting diode, a second electrode layer, an encapsulation layer and a driver circuit. The light emitting diode includes a red light emitting layer, a green light emitting layer and a blue light emitting layer which includes a silicon-germanium quantum dot material.

Abstract: A display apparatus having a display area and a pad area and a method of manufacturing the same, the display apparatus including a base substrate; a thin film transistor on the base substrate in the display area; an insulation layer on the base substrate and the thin film transistor; a conductive pattern layer on the insulation layer, the conductive pattern layer including a pad electrode in the pad area; and a via insulation layer on the insulation layer, exposing an upper surface of the pad electrode, and covering edges of the pad electrode, wherein, in the pad area, the insulation layer includes a groove having a depth, the pad electrode being in the groove.

Abstract: A system and method for creating various dopant concentration profiles using a single implant energy is disclosed. A plurality of implants are performed at the same implant energy but different tilt angles to implant ions at a variety of depths. The result of these implants may be a rectangular profile or a gradient profile. The resulting dopant concentration profile depends on the selection of tilt angles, doses and the number of implants. Varying tilt angle rather than varying implant energy to achieve implants of different depths may significantly improve efficiency and throughput, as the tilt angle can be changed faster than the implant energy can be changed. Additionally, this method may be performed by a number of different semiconductor processing apparatus.

Abstract: The present disclosure provides a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a substrate, a word line, a plurality of first impurity regions, a second impurity region, and an isolation film. The word line is W-shaped, is disposed in the substrate, and includes a base and a pair of legs connected to the base. The first impurity regions are disposed in the substrate and on either side of the word line. The second impurity region is disposed between the legs of the word line. The isolation film is disposed in the substrate, wherein the word line is surrounded by the isolation film.

Abstract: One illustrative Schottky diode disclosed herein includes a semiconductor substrate, an anode region and a cathode region. The anode region includes a plurality of first fins with a first vertical height formed in the anode region, wherein an upper surface of the semiconductor substrate is exposed within the anode region. The cathode region includes a plurality of second fins with a second vertical height that is greater than the first vertical height. The device also includes a conductive structure that contacts and engages at least an upper surface of the plurality of first fins in the anode region.

Abstract: Apparatus and other embodiments associated with high speed and high breakdown voltage MOS rectifier are disclosed. A Junction All Around structure, where a deep trench structure surrounds and encloses a P-N junction or a MOS structure, is created and applied in various rectifiers. In one embodiment, multiple deep trenches in concentric ring circles enclosed several horizontal P-N junctions in concentric ring circles. In another embodiment, an enclosed deep trench in ring circle surrounds a horizontal P-N junction, which results in a planar N-channel MOS during forward bias. This structure can be extended to multiple deep trenches with associated horizontal P-N junctions.

Abstract: A display device comprising: pixel electrodes; an electroluminescent layer composed of layers laminated with each other, the multiple layers including a light-emitting layer and a charge generation layer; and a counter electrode. The multiple layers include a first layer composed of sections separated from each other and overlapping with the pixel electrodes, a second layer in contact with the first layer and continuous over the pixel electrodes, and a third layer interposed between the first layer and the second layer, the third layer being in contact with the first layer and the second layer over an adjacent pair of the sections. At least the charge generation layer is the first layer. The second layer is adapted to inject or transport carriers, either electrons or holes. The third layer is adapted to block the carriers injected or transported by the second layer.

Abstract: Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a base; a fin extending away from the base, wherein the fin includes a quantum well layer; an insulating material at least partially above the fin, wherein the insulating material includes a trench above the fin; and a gate metal on the insulating material and extending into the trench.

Abstract: An electronic device comprises a channel layer on a buffer layer on a substrate. The channel layer has a first portion and a second portion adjacent to the first portion. The first portion comprises a first semiconductor. The second portion comprises a second semiconductor that has a bandgap greater than a bandgap of the first semiconductor.

Abstract: A bipolar junction transistor (BJT) may include a substrate defining a collector region therein. A first superlattice may be on the substrate including a plurality of stacked groups of first layers, with each group of first layers including a first plurality of stacked base semiconductor monolayers defining a first base semiconductor portion, and at least one first non-semiconductor monolayer constrained within a crystal lattice of adjacent first base semiconductor portions. Furthermore, a base may be on the first superlattice, and a second superlattice may be on the base including a second plurality of stacked groups of second layers, with each group of second layers including a plurality of stacked base semiconductor monolayers defining a second base semiconductor portion, and at least one second non-semiconductor monolayer constrained within a crystal lattice of adjacent second base semiconductor portions. An emitter may be on the second superlattice.

Abstract: A wide gap semiconductor device has: a drift layer using wide gap semiconductor material being a first conductivity type; a well region being a second conductivity type and provided in the drift layer; a source region provided in the well region; a gate contact region provided in the well region and electrically connected to a gate pad; and a Zener diode region provided in the well region and provided between the source region and the gate contact region.