Abstract: Semiconductor devices and methods of manufacture are provided wherein a metallization layer is located over a substrate, and a power grid line is located within the metallization layer. A signal pad is located within the metallization layer and the signal pad is surrounded by the power grid line. A signal external connection is electrically connected to the signal pad.

Abstract: A display device includes a substrate having a display area, a peripheral area at least partially surrounding the display area, and a pad area within the peripheral area. A plurality of data lines is disposed within the display area. A plurality of connection wirings is disposed within the display area, connected to the plurality of data lines, and configured to transmit a data signal from the pad area to the plurality of data lines. Each of the plurality of connection wirings includes a plurality of branches that protrude from the connection wirings in a direction perpendicular to a direction in which the connection wirings are primarily extended.

Abstract: Provided are a method of manufacturing a display device and a source substrate structure. The method of manufacturing the display device includes holding a light-emitting element on a source substrate that passes laser light of a certain wavelength therethrough, the holding being performed by a release layer between the source substrate and the light-emitting element, forming an adhesive layer on a driving substrate on which a driving substrate-side electrode is formed, moving the light-emitting element to a surface of the adhesive layer on the driving substrate from the source substrate by irradiating laser light of the certain wavelength to the release layer through the source substrate, and adhering the moved light-emitting element to the driving substrate by using the adhesive layer, and the release layer comprises a resin material with a thickness that is greater than or equal to 0.1 ?m and is less than or equal to 0.5 ?m.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed herein. An exemplary semiconductor device comprises a semiconductor fin disposed over a substrate, wherein the semiconductor fin includes a channel region and a source/drain region; a gate structure disposed over the channel region of the semiconductor fin, wherein the gate structure includes a gate spacer and a gate stack; a source/drain structure disposed over the source/drain region of the semiconductor fin; and a fin top hard mask vertically interposed between the gate spacer and the semiconductor fin, wherein the fin top hard mask includes a dielectric layer, and wherein a sidewall of the fin top hard mask directly contacts the gate stack, and another sidewall of the fin top hard mask directly contacts the source/drain structure.

Abstract: Systems, methods and apparatus are provided for an array of vertically stacked memory cells having horizontally oriented access devices and access lines and vertically oriented digit lines having a first source/drain region and a second source drain region separated by a channel region, and gates opposing the channel region formed fully around every surface of the channel region as gate all around (GAA) structures, horizontal oriented access lines coupled to the gates and separated from a channel region by a gate dielectric. The memory cells have horizontally oriented storage nodes coupled to the second source/drain region and vertically oriented digit lines coupled to the first source/drain regions. A vertical body contact is formed in direct electrical contact with a body region of one or more of the horizontally oriented access devices and separate from the first source/drain region and the vertically oriented digit lines by a dielectric.

Abstract: A semiconductor device. In some embodiments, the semiconductor device includes a back gate layer; a buffer layer, on the back gate layer; a device quantum well layer, on the buffer layer; a cap layer, on the device quantum well layer; a top layer, on the cap layer; a first doped region of a first conductivity type, extending at least part-way through the device quantum well layer; a second doped region, of a second conductivity type, within the buffer layer; and a third doped region, of the second conductivity type extending from the top layer to the second doped region. The top layer may include a dielectric layer, and, in the dielectric layer, a plurality of conductive elements, including one or more dot gates, an ohmic contact, a bath gate, a supply gate, and a halo contact.

Abstract: One illustrative transistor of a first dopant type disclosed herein includes a gate structure positioned above a semiconductor substrate and first and second overall epitaxial cavities formed in the semiconductor substrate on opposite sides of the gate structure. The device also includes a counter-doped epitaxial semiconductor material positioned proximate a bottom of each of the first and second overall epitaxial cavities, wherein the counter-doped epitaxial semiconductor material is doped with a second dopant type that is opposite to the first dopant type, and a same-doped epitaxial semiconductor material positioned in each of the first and second overall epitaxial cavities above the counter-doped epitaxial semiconductor material, wherein the same-doped epitaxial semiconductor material is doped with a dopant of the first dopant type.

Abstract: A process for fabricating an electronic component with multiple quantum dots is provided, including providing a stack including a substrate, a nanostructure made of semiconductor material superposed over the substrate and including first and second quantum dots and a link linking the quantum dots, first and second control gate stacks arranged on the quantum dots, the gate stacks separated by a gap, the quantum dots and the link having a same thickness; partially thinning the link while using the gate stacks as masks to obtain the link, a thickness of which is less than that of the quantum dots; and conformally forming a dielectric layer on either side of the gate stacks so as to fill the gap above the partially thinned link. An electronic component with multiple quantum dots is also provided.

Abstract: Provided is an organic light-emitting diode. The organic light-emitting diode includes a first electrode, a second electrode, a light-emitting layer and a hole blocking layer, where the first electrode and the second electrode are oppositely disposed; the light-emitting layer is disposed between the first electrode and the second electrode; the hole blocking layer is disposed between the light-emitting layer and the second electrode; and the hole blocking layer includes at least two hole blocking sub-layers which are stacked, where a lowest unoccupied molecular orbital (LUMO) energy level decreases sequentially in the at least two hole blocking sub-layers.

Abstract: The present application provides an organic electroluminescent device and a display apparatus. The organic electroluminescent device includes a first conductive layer group, a second conductive layer group, and a light emitting layer disposed between the first conductive layer group and the second conductive layer group and in ohmic contact with the two groups. The first conductive layer group includes an electron blocking layer in ohmic contact with the light emitting layer, and a hole transport layer in ohmic contact with the electron blocking layer. The HOMO energy level of the electron blocking layer is between that of the hole transport layer and that of the light emitting layer, and the LUMO energy level of the electron blocking layer is shallower than that of the hole transport layer and that of the light emitting layer.

Abstract: A power module, including: a first conductor, disposed at a first reference plane; a second conductor, disposed at a second reference plane, wherein projections of the first and second conductors on the first reference plane have a first overlap area; a third conductor, disposed at a third reference plane; a plurality of first switches, first ends of which are coupled to the first conductor; and a plurality of second switches, first ends of which are coupled to second ends of the first switches through the third conductor, and second ends of the second switches are coupled to the second conductor, wherein projections of minimum envelope areas of the first and second switches on the first reference plane have a second overlap area, and the first and second overlap areas have an overlap region. Heat sources of the power module are evenly distributed and its parasitic inductance is low.

Abstract: According to one embodiment, a semiconductor device includes first, second and third electrodes, first and second semiconductor layers, first and second insulating members, and a first member. The third electrode includes a first electrode portion. The first electrode portion is between the first and second electrodes. The first semiconductor layer includes first, second, third, fourth, and fifth partial regions. The fourth partial region is between the first and third partial regions. The fifth partial region is between the third and second partial regions. The first insulating member includes first and second insulating regions. The second insulating member includes first and second insulating portions. The first insulating portion is between the fourth partial region and the first insulating region. The second insulating portion is between the fifth partial region and the second insulating region. The second semiconductor layer includes first, second, and third semiconductor portions.

Abstract: A semiconductor device structure is provided, which includes a first fin structure over a semiconductor substrate. The first fin structure has multiple first semiconductor nanostructures suspended over the semiconductor substrate. The semiconductor device structure includes a second fin structure over the semiconductor substrate, and the second fin structure has multiple second semiconductor nanostructures suspended over the semiconductor substrate. The semiconductor device structure includes a dielectric fin between the first fin structure and the second fin structure. In addition, the semiconductor device structure includes a metal gate stack wrapping around the first fin structure, the second fin structure, and the dielectric fin. The semiconductor device structure includes a dielectric protection structure over the metal gate stack.

Abstract: There is provided a light emitting device including: a substrate; and a laminated structure provided on the substrate and having a plurality of columnar portion groups, in which the columnar portion group includes at least one first columnar portion, and a plurality of second columnar portions, the first columnar portion has a light emitting layer into which a current is injected to generate light, no current is injected into the second columnar portion, an optical confinement mode is formed in the plurality of columnar portion groups, the first columnar portion is disposed at a position that overlaps a peak of electric field intensity, and the second columnar portion is disposed at a position that does not overlap the peak of electric field intensity.

Abstract: Apparatus and other embodiments associated with high speed and high breakdown voltage MOS rectifier are disclosed. A Junction All Around structure, where a deep trench structure surrounds and encloses a P-N junction or a MOS structure, is created and applied in various rectifiers. In one embodiment, an enclosed deep trench in ring shape surrounds a vertical MOS structure plus a shallow trench gate in the center to create a device with very high breakdown voltage and very low leakage current. This structure is extended to multiple deep trenches and shallow trenches alternating each other.

Abstract: A semiconductor device includes a base structure including a lower level via and a lower level dielectric layer, a conductive pillar including an upper level line and an upper level via disposed on the lower level via, and a protective structure disposed between the lower level via and the upper level line. The protective structure includes a material having an etch rate less than or equal to that of the lower level via.

Abstract: A method includes providing a semiconductor substrate; epitaxially growing a blocking layer from a top surface of the semiconductor substrate, wherein the blocking layer has a lattice constant different from the semiconductor substrate; epitaxially growing a semiconductor layer above the blocking layer; patterning the semiconductor layer to form a semiconductor fin, wherein the blocking layer is under the semiconductor fin; forming a source/drain (S/D) feature in contact with the semiconductor fin; and forming a gate structure engaging the semiconductor fin.

Abstract: Provided are a tin oxide layer, a thin film transistor (TFT) having the same as a channel layer, and a method for manufacturing the TFT. The TFT comprises a gate electrode, a tin oxide channel layer disposed on the gate electrode and being a polycrystalline thin film with preferred orientation in a [001] direction, a gate insulating film disposed between the gate electrode and the channel layer, and source and drain electrodes electrically connected to both ends of the channel layer, respectively.

Abstract: An integrated circuit includes an active zone having a center portion adjoining a first side portion and a second side portion. A first transistor having a gate formed over one of the first channel regions in the center portion has a first threshold-voltage. A second transistor having a gate formed over one of the second channel regions in the center portion has a second threshold-voltage. A third transistor having a gate formed over one of the third channel regions in the first side portion has a third threshold-voltage. A fourth transistor having a gate formed over one of the fourth channel regions in the second side portion has a fourth threshold-voltage. A first average of the first threshold-voltage and the second threshold-voltage is larger than a second average of the third threshold-voltage and the fourth threshold-voltage by a predetermined threshold-voltage offset.

Abstract: The present invention relates to organic electroluminescent devices comprising a light-emitting layer B comprising a host material, a phosphorescence material and a emitter material, which exhibits a narrow—expressed by a small full width at half maximum (FWHM)—green emission at an emission maximum of 500 to 560 nm. Further, the present invention relates to a method for generating green light by means of an organic electroluminescent device according to the present invention.