Abstract: There is provided a light emitting device including: a substrate; and a laminated structure provided on the substrate and having a plurality of columnar portion groups, in which the columnar portion group includes at least one first columnar portion, and a plurality of second columnar portions, the first columnar portion has a light emitting layer into which a current is injected to generate light, no current is injected into the second columnar portion, an optical confinement mode is formed in the plurality of columnar portion groups, the first columnar portion is disposed at a position that overlaps a peak of electric field intensity, and the second columnar portion is disposed at a position that does not overlap the peak of electric field intensity.

Abstract: Apparatus and other embodiments associated with high speed and high breakdown voltage MOS rectifier are disclosed. A Junction All Around structure, where a deep trench structure surrounds and encloses a P-N junction or a MOS structure, is created and applied in various rectifiers. In one embodiment, an enclosed deep trench in ring shape surrounds a vertical MOS structure plus a shallow trench gate in the center to create a device with very high breakdown voltage and very low leakage current. This structure is extended to multiple deep trenches and shallow trenches alternating each other.

Abstract: A semiconductor device includes a base structure including a lower level via and a lower level dielectric layer, a conductive pillar including an upper level line and an upper level via disposed on the lower level via, and a protective structure disposed between the lower level via and the upper level line. The protective structure includes a material having an etch rate less than or equal to that of the lower level via.

Abstract: A method includes providing a semiconductor substrate; epitaxially growing a blocking layer from a top surface of the semiconductor substrate, wherein the blocking layer has a lattice constant different from the semiconductor substrate; epitaxially growing a semiconductor layer above the blocking layer; patterning the semiconductor layer to form a semiconductor fin, wherein the blocking layer is under the semiconductor fin; forming a source/drain (S/D) feature in contact with the semiconductor fin; and forming a gate structure engaging the semiconductor fin.

Abstract: Provided are a tin oxide layer, a thin film transistor (TFT) having the same as a channel layer, and a method for manufacturing the TFT. The TFT comprises a gate electrode, a tin oxide channel layer disposed on the gate electrode and being a polycrystalline thin film with preferred orientation in a [001] direction, a gate insulating film disposed between the gate electrode and the channel layer, and source and drain electrodes electrically connected to both ends of the channel layer, respectively.

Abstract: An integrated circuit includes an active zone having a center portion adjoining a first side portion and a second side portion. A first transistor having a gate formed over one of the first channel regions in the center portion has a first threshold-voltage. A second transistor having a gate formed over one of the second channel regions in the center portion has a second threshold-voltage. A third transistor having a gate formed over one of the third channel regions in the first side portion has a third threshold-voltage. A fourth transistor having a gate formed over one of the fourth channel regions in the second side portion has a fourth threshold-voltage. A first average of the first threshold-voltage and the second threshold-voltage is larger than a second average of the third threshold-voltage and the fourth threshold-voltage by a predetermined threshold-voltage offset.

Abstract: The present invention relates to organic electroluminescent devices comprising a light-emitting layer B comprising a host material, a phosphorescence material and a emitter material, which exhibits a narrow—expressed by a small full width at half maximum (FWHM)—green emission at an emission maximum of 500 to 560 nm. Further, the present invention relates to a method for generating green light by means of an organic electroluminescent device according to the present invention.

Abstract: A display substrate having an array of a plurality of subpixels is provided. The display substrate includes a base substrate; a pixel driving layer including a plurality of thin film transistors on the base substrate; a tuning layer on a side of the pixel driving layer away from the base substrate, thicknesses of the tuning layer being different in subpixels of different colors; and a plurality of organic light emitting diodes on a side of the tuning layer away from the pixel driving layer. A respective one of the plurality of organic light emitting diodes includes a hole injection layer, thicknesses of the hole injection layer being different in subpixels of different colors. The thicknesses of the tuning layer and the thicknesses of the hole injection layer are negatively correlated among the subpixels of different colors.

Abstract: A semiconductor sensor includes a source element; a drain element; and a semiconductor channel element between the source element and the drain element, forming an electrically conductive channel. An insulator is positioned between the semiconductor channel element and a solution to be sensed. A reference contacts the solution and sets an electric potential of the solution. A bias voltage source generates an external sensor bias voltage for electrically biasing the reference electrode. A sensing surface interacts with the solution comprising analytes for generating a surface potential change at the sensing surface dependent on the concentration of analytes. The sensor further includes a ferroelectric capacitance element between the insulator and the bias voltage source for generating a negative capacitance for a differential gain between the external sensor bias voltage and an internal sensor bias voltage sensed at a surface of the channel element facing the insulator or ferroelectric capacitance element.

Abstract: A pressure sensing unit includes: a first substrate and a second substrate opposite to each other; and at least one vertical thin film transistor disposed between the first substrate and the second substrate. Each vertical thin film transistor includes a first electrode, a semiconductor active layer, a second electrode, at least one insulating support, and a gate electrode sequentially disposed in a direction extending from the first substrate to the second substrate. A first air gap is formed by the presence of the at least one insulating support between the gate electrode and the second electrode of each vertical thin film transistor.

Abstract: Methods and structures for forming vias are provided. The method includes forming a structure that includes an odd line hardmask and an even line hardmask. The odd line hardmask and the even line hardmask include different hardmask materials that have different etch selectivity with respect to each other. The method includes patterning vias separately into the odd line hardmask and the even line hardmask based on the different etch selectivity of the different hardmask materials. The method also includes forming via plugs at the vias. The method includes cutting even line cuts and odd line cuts into the structure. The even line cuts and the odd line cuts are self-aligned with the vias. The vias are formed at line ends of the structure.

Abstract: The present application provides an integrated semiconductor device and an electronic apparatus, comprising a semiconductor substrate and a first doped epitaxial layer having a first region, a second region, and a third region; a partition structure is arranged in the third region; the first region is formed having at least two second doped deep wells, and the second region is formed having at least two second doped deep wells; a dielectric island partially covers a region between two adjacent doped deep wells in the first region and second region; a gate structure covers the dielectric island; a first doped source region is located on the two sides of the gate structure, and a first doped source region located in the same second doped deep well is separated; a first doped trench is located on the two sides of the dielectric island in the first region, and extends laterally to the first doped source region.

Abstract: A chip part includes a chip main body which has a first main surface at one side, a second main surface at the other side and side surfaces that connect the first main surface and the second main surface and which includes a terminal electrode exposed from the first main surface, and an outer surface resin which exposes the first main surface of the chip main body and covers an outer surface of the chip main body.

Abstract: A package structure and method of forming the same are provided. The package structure includes a die, a TIV, an encapsulant, an adhesion promoter layer, a RDL structure and a conductive terminal. The TIV is laterally aside the die. The encapsulant laterally encapsulates the die and the TIV. The adhesion promoter layer is sandwiched between the TIV and the encapsulant. The RDL structure is electrically connected to the die and the TIV. The conductive terminal is electrically connected to the die through the RDL structure.

Abstract: A semiconductor device includes: a semiconductor layer formed on a substrate; a first resin layer formed on the semiconductor layer; a second resin layer formed on the first resin layer; a first wiring layer that is formed on the semiconductor layer and is buried in the second resin layer; a second wiring layer that is formed on the second resin layer and the first wiring layer, and is electrically connected to the first wiring layer; and a first inorganic insulating film covering the second resin layer and the second wiring layer, wherein an area of the first wiring layer is larger than an area of the second wiring layer.

Abstract: A method of fabricating semiconductor devices includes forming a plurality of first and second semiconductor nanosheets in p-type and n-type device regions, respectively. An n-type work function layer is deposited to surround each of the first and second semiconductor nanosheets. A passivation layer is deposited on the n-type work function layer to surround each of the first and second semiconductor nanosheets. A patterned mask is formed on the passivation layer in the n-type device region, and the n-type work function layer and the passivation layer in the p-type device region are removed in an etching process using the patterned mask as an etching mask. Then, the patterned mask is removed, and a p-type work function layer is deposited to surround the first semiconductor nanosheets and to cover the passivation layer.

Abstract: A semiconductor device includes a gate structure disposed over a channel region, a source/drain epitaxial layer disposed at a source/drain region, a nitrogen containing layer disposed on the source/drain epitaxial layer, a silicide layer disposed on the nitrogen containing layer, and a conductive contact disposed on the silicide layer.

Abstract: Semiconductor device and method of forming a semiconductor device are provided. A substrate is provided, and first gate structures and source/drain doped layers are formed on the substrate. A dielectric layer is formed on the substrate, covering the first gate structures and source/drain doped layers. A first groove is formed in the dielectric layer exposing the source/drain doped layer. The first groove includes a first-groove bottom part and a first-groove top part. The first-groove top part is larger than the first-groove bottom part, and a sidewall of the first-groove top part is recessed more into the dielectric layer with respect to a sidewall of the first-groove bottom part. A first conductive structure is formed in the first-groove bottom part, and an insulating layer is formed in the first-groove top part. A second conductive structure, connected to the first gate structure, is formed in the dielectric layer.

Abstract: A low specific on-resistance (Ron,sp) power semiconductor device includes a power device and a transient voltage suppressor (TVS); wherein the power device comprises a gate electrode, a drain electrode, a bulk electrode, a source electrode and a parasitic body diode, the bulk electrode and the source electrode are shorted, the TVS comprises an anode electrode and a cathode electrode, the drain electrode of the power device and the anode electrode of the TVS are connected by a first metal to form a high-voltage terminal electrode, the source electrode of the power device and the cathode electrode of the TVS are connected by a second metal to form a low-voltage terminal electrode.

Abstract: Provided is a solid-state imaging device including a first substrate that includes a pixel unit, a first semiconductor substrate, and a first multi-layered wiring layer stacked, a second substrate that includes circuit, a second semiconductor substrate, and a second multi-layered wiring layer stacked, the circuit having a predetermined function, a third substrate that includes a circuit, a third semiconductor substrate, and a third multi-layered wiring layer. The first substrate and the second substrate being bonded together such that the first multi-layered wiring layer is opposite to the second semiconductor substrate, and a first coupling structure for electrically coupling the circuit of the first substrate with the circuit of the second substrate, the first coupling structure is on bonding surfaces of the first substrate and the second substrate, and includes an electrode junction structure in which electrodes on the respective bonding surfaces are joined to each other in direct contact.