Abstract: A method for packaging a thermoelectric module may include thermoelectric module accommodation, of accommodating at least one thermoelectric module in a housing having a base and a sidewall, electric wire sealing, of sealing an electric wire of the thermoelectric module with a sealing tube, bonding member interposing, of placing a cover having a top portion and a sidewall on top of the housing and interposing a bonding member between the sidewall of the housing and the sidewall of the cover, and bonding, of bonding the sidewall of the housing and the sidewall of the cover that are hermetically sealed by the bonding member, in which the bonding member may be formed of a resin material.

Abstract: Silicon oxide layer is deposited on a semiconductor substrate by PECVD at a temperature of less than about 200° C. and is treated with helium plasma to reduce stress of the deposited layer to an absolute value of less than about 80 MPa. Plasma treatment reduces hydrogen content in the silicon oxide layer, and leads to low stress films that can also have high density and low roughness. In some embodiments, the film is deposited on a semiconductor substrate that contains one or more temperature-sensitive layers, such as layers of organic material or spin-on dielectric that cannot withstand temperatures of greater than 250° C. In some embodiments the silicon oxide film is deposited to a thickness of between about 100-200 ?, and is used as a hardmask layer during etching of other layers on a semiconductor substrate.

Abstract: According to one embodiment, a first stacked body in which first insulation layers and second insulation layers are alternately stacked is formed, a first hole penetrating through the first stacked body is formed, a sacrifice film is embedded in the first hole, the sacrifice film is protruded from the first stacked body to form a protrusion portion on the first stacked body, a second stacked body in which third insulation layers and fourth insulation layers are alternately stacked is formed on the first stacked body, and a second hole penetrating through the second stacked body is formed.

Abstract: A packaged electronic system comprises a slab (210) of low-grade silicon (l-g-Si) configured as ridges (114) framing a depression of depth (112) including a recessed central area suitable to accommodate semiconductor chips and embedded electrical components, the depth at least equal to the thickness of the chips and the components, the ridge covered by system terminals (209b) connected to attachment pads in the central area; and semiconductor chips (120, 130) having a thickness and terminals on at least one of opposing chip sides, the chips terminals attached to the central area terminals so that the opposite chip side is coplanar with the system terminals on the slab ridge.

Abstract: A method of manufacturing a semiconductor device includes providing a substrate having an insulating film and a plurality of conductive films on a surface; reducing the substrate by supplying a first reducing gas to the substrate so that at least one of a plurality of process conditions of the first reducing gas is controlled so that a product of a plurality of process conditions becomes a predetermined value, wherein the process conditions of the first reducing gas include a partial pressure of the first reducing gas in a region where the substrate exists and a time taken to supply the first reducing gas to the substrate corresponding to a temperature of the first reducing gas; and selectively forming a metal film on the plurality of the reduced conductive films by supplying a second reducing gas and a metal-containing gas to the substrate.

Abstract: The present invention provides a method for forming an opening, including: first, a hard mask material layer is formed on a target layer, next, a tri-layer hard mask is formed on the hard mask material layer, where the tri-layer hard mask includes an bottom organic layer (ODL), a middle silicon-containing hard mask bottom anti-reflection coating (SHB) layer and a top photoresist layer, and an etching process is then performed, to remove parts of the tri-layer hard mask, parts of the hard mask material layer and parts of the target layer in sequence, so as to form at least one opening in the target layer, where during the step for removing parts of the hard mask material layer, a lateral etching rate of the hard mask material layer is smaller than a lateral etching rate of the ODL.

Abstract: According to one embodiment, a method for manufacturing a semiconductor memory device includes forming a mask layer on the stacked body. The method includes forming a stopper film in a part of the mask layer. The method includes forming a plurality of mask holes in the mask layer. The mask holes include a first mask hole overlapping on the stopper film. The method includes, by etching using the mask layer, forming holes in the stacked body under other mask holes than the first mask hole on the stopper film, but not forming holes in the stacked body under the stopper film. The method includes forming memory films and channel bodies in the holes.

Abstract: There is configured a solid-state imaging unit including: a semiconductor base 21 having one surface serving as a circuit formation surface and another surface serving as a light receiving surface; a photoelectric conversion section 22 provided in the semiconductor base 21; a reflection layer 24 provided on the circuit formation surface above the photoelectric conversion section 22; and an insulating section 23 arranged in the reflection layer 24.

Abstract: Embodiments pin connections, electronic devices, and methods are shown that include pin configurations to reduce voids and pin tilting and other concerns during pin attach operations, such as attachment to a chip package pin grid array. Pin head are shown that include features such as convex surfaces, a number of legs, and channels in pin head surfaces.

Abstract: A method for manufacturing a light-emitting device includes providing a soluble member to cover at least one lateral surface of a light-emitting element. The soluble member includes a material soluble in a first solvent. A light-shielding member is provided to cover at least one lateral surface of the soluble member. The light-shielding member includes a light-shielding resin less soluble in the first solvent than the soluble member. The soluble member is removed with the first solvent. A first light-transmissive member is provided in a space formed by removing the soluble member.

Abstract: In a first aspect, the present disclosure provides a method of forming a semiconductor device, including providing an SOI structure comprising a base substrate, a buried insulating material layer formed on the base substrate and an active semiconductor layer formed on the buried insulating structure, forming a germanium-comprising layer on an exposed surface of the active semiconductor layer, forming a trench isolation structure, the trench isolation structure extending through the germanium-comprising layer and the active semiconductor layer, performing an annealing process after the trench isolation structure is formed, the annealing process resulting in an oxide layer disposed on a germanium-comprising active layer which is formed on the buried insulating material layer, and removing the oxide layer for exposing an upper surface of the germanium-comprising active layer.

Abstract: In accordance with embodiments disclosed herein, there are provided methods and systems for implementing damage-and-resist-free laser patterning of dielectric films on textured silicon. For example, in one embodiment, such means include means for depositing a Silicon nitride (SiNx) or SiOx (silicon oxide) layer onto a crystalline silicon (c-Si) substrate by a Plasma Enhanced Chemical Vapor Deposition (PECVD) processing; depositing an amorphous silicon (a-Si) film on top of the SiNx or SiOx layer; patterning the a-Si film to define an etch mask for the SiNx or SiOx layer; removing the SiNx or SiOx layer via a Buffered Oxide Etch (BOE) chemical etch to expose the c-Si surface; removing the a-Si mask with a hydrogen plasma etch in a PECVD tool to prevent current loss from the mask; and plating the exposed c-Si surface with metal contacts. Other related embodiments are disclosed.

Abstract: The present disclosure generally relates to methods for removing contaminants and native oxides from substrate surfaces. The method includes exposing a surface of the substrate to first hydrogen radical species, wherein the substrate is silicon germanium having a concentration of germanium above about 30%, then exposing the surface of the substrate to a plasma formed from a fluorine-containing precursor and a hydrogen-containing precursor, and then exposing the surface of the substrate to second hydrogen radical species.

Abstract: A method for fabricating a stacked thin film transistor (TFT) structure comprises: forming at least two TFTs on a substrate of a display device; at least partially covering the at least two TFTs with an insulating layer; forming a common electrode on the insulating layer and the at least two TFTs; covering, at least partially, the common electrode with a dielectric material, wherein the insulating layer, the common electrode, and the dielectric material each include a contact hole; filling, at least partially, the contact hole with a conductive material; and depositing the conductive material over the dielectric material to form a pixel electrode.

Abstract: A packaged transistor device (100) comprises a semiconductor chip (101) including a transistor with terminals distributed on the first and the opposite second chip side; and a slab (110) of low-grade silicon (l-g-Si) configured as a ridge (111) framing a depression including a recessed central area suitable to accommodate the chip, the ridge having a first surface in a first plane and the recessed central area having a second surface in a second plane spaced from the first plane by a depth (112) at least equal to the chip thickness, the ridge covered by device terminals (120; 121) connected to attachment pads in the central area having the terminals of the first chip side attached so that the terminals (103) of the opposite second chip side are co-planar with the device terminals on the slab ridge.

Abstract: A semiconductor device includes a substrate having a field region disposed therein that defines an active region of the substrate, the active region comprising a pillar-shaped bit line contact region having an upper surface disposed at a higher level than an upper surface of the field region. An interlayer insulating layer is disposed on the substrate and covers the field region. A bit line is disposed in a trench in the interlayer insulating layer above the pillar-shaped bit line contact region and electrically connected thereto.

Abstract: Disclosed herein is a method of forming a CMOS integrated circuit product (comprised of first and second opposite type transistors) that includes forming a first spacer proximate both the first and second gate structures, forming an initial second spacer proximate the first spacer of the first transistor and a layer of second spacer material above the second transistor, and forming first raised epi semiconductor material source/drain regions for the first transistor. Thereafter, performing a first surface oxidation process so as to selectively form a hydrophilic material on exposed surfaces of the first raised epi semiconductor material and performing an etching process on both the transistors so as to remove the initial second spacer and the layer of second spacer material.

Abstract: A three-dimensional (3D) integrated circuit (IC) includes a plurality of through silicon vias (TSVs) configured to provide paths via which digital signals are transmitted or received; at least one redundant TSV configured to provide a path via which a digital signal to be transmitted or received via a failed TSV with a defect among the plurality of TSVs is transmitted or received; a digital-to-analog converter (DAC) configured to convert a digital signal transmitted via the at least one redundant TSV into an analog signal; an analog-to-digital converter (ADC) configured to convert an analog signal received via the at least one redundant TSV into a digital signal; and a multilevel modulator configured to perform multilevel modulation on a digital signal transmitted via the at least one redundant TSV.

Abstract: Disclosed is a thin film transistor array panel including: a substrate including a display area and a peripheral area; a second semiconductor layer disposed on the substrate, and disposed on a first semiconductor layer disposed in the display area and the peripheral area; and a passivation layer disposed on the first semiconductor layer and the second semiconductor layer, wherein the first semiconductor layer and the second semiconductor layer include an oxide semiconductor, and a thickness of the first semiconductor layer is different from that of the second semiconductor layer.

Abstract: A method of fabricating a vertical transistor is provided, the method including providing a starting semiconductor structure, the starting semiconductor structure including a semiconductor substrate, an impurity layer of n-type or p-type over the semiconductor substrate, a first hard mask layer over the semiconductor layer, a first dielectric layer over the first hard mask layer, a second hard mask layer over the first dielectric layer, a second dielectric layer over the second hard mask layer and a protective layer over the second dielectric layer. The method further includes patterning the second dielectric layer and protective layer, the patterning forming an opening therein, forming a wrap-around spacer on an inner sidewall of the opening, the forming leaving a smaller opening, forming a vertical channel, and setting a gate length of a wrap-around gate by removing an outer portion of the structure.