Abstract: A method for etching features with different aspect ratios in an etch layer is provided. A plurality of cycles is provided wherein each cycle comprises a pre-etch transient conditioning of the etch layer, which provides a transient condition of the etch layer, wherein the transient condition has a duration and etching the etch layer for a duration, wherein the duration of the etching with respect to the duration of the transient condition is controlled to control etch aspect ratio dependence.

Abstract: Embodiments pin connections, electronic devices, and methods are shown that include pin configurations to reduce voids and pin tilting and other concerns during pin attach operations, such as attachment to a chip package pin grid array. Pin head are shown that include features such as convex surfaces, a number of legs, and channels in pin head surfaces.

Abstract: A method of manufacturing a solar cell comprising steps of: (a) preparing a substrate comprising a semiconductor layer and a passivation layer formed at least on the back side of the semiconductor layer, wherein the passivation layer on the back side comprises one or more openings; (b) forming an aluminum (Al) conductor pattern at least in the openings of the passivation layer on the back side by applying an Al paste, wherein the Al paste comprises: (i) an Al powder, (ii) a glass frit, (iii) a zirconium carbide (ZrC) powder, and (iv) an organic medium; and (c) firing the Al conductor pattern.

Abstract: A tape film package is provided including an insulating pattern; a via contact in a via hole in the insulating pattern; first interconnection patterns extending from the via contact to a cutting surface of the insulating pattern; and second interconnection patterns connected to the via contact below the insulating pattern. The second interconnection patterns are parallel to the first interconnection patterns and spaced apart from the cutting surface of the insulating pattern.

Abstract: A semiconductor structure includes a III-nitride substrate with a first side and a second side opposing the first side. The III-nitride substrate is characterized by a first conductivity type and a first dopant concentration. The semiconductor structure further includes a III-nitride epitaxial layer of the first conductivity type coupled to the first surface of the III-nitride substrate, a first metallic structure electrically coupled to the second surface of the III-nitride substrate, and a III-nitride epitaxial structure of a second conductivity type coupled to the III-nitride epitaxial layer. The III-nitride epitaxial structure comprises at least one edge termination structure.

Abstract: Embodiments described herein generally relate to landing gate pads for contacts and manufacturing methods therefor. A bridge is formed between two features to allow a contact to be disposed, at least partially, on the bridge. Landing the contact on the bridge avoids additional manufacturing steps to create a target for a contact.

Abstract: A semiconductor device includes a semiconductor chip including a first main face and a second main face. The second main face is the backside of the semiconductor chip. The second main face includes a first region and a second region. The second region is a peripheral region of the second main face and the level of the first region and the level of the second region are different. The first region may be filled with metal and may be planarized to the same level as the second region.

Abstract: A power device includes a chip of semiconductor material and a further chip of semiconductor material on each of which at least one power transistor is integrated; each chip comprises a first conduction terminal on a first surface, and a second conduction terminal and a control terminal on a second surface opposite the first surface, and an insulating body embedding said chip and said further chip. In the solution according to one or more embodiments of the present disclosure, the first surface of said chip faces the second surface of said further chip, and the power device further comprises a first heat-sink arranged between said chip and said further chip and electrically coupled with the first conduction terminal of said chip and with the second conduction terminal of said further chip, the control terminal of said further chip being electrically insulated from the first heat-sink.

Abstract: A semiconductor structure includes a III-nitride substrate characterized by a first conductivity type and having a first side and a second side opposing the first side, a III-nitride epitaxial layer of the first conductivity type coupled to the first side of the III-nitride substrate, and a plurality of III-nitride epitaxial structures of a second conductivity type coupled to the III-nitride epitaxial layer. The semiconductor structure further includes a III-nitride epitaxial formation of the first conductivity type coupled to the plurality of III-nitride epitaxial structures, and a metallic structure forming a Schottky contact with the III-nitride epitaxial formation and coupled to at least one of the plurality of III-nitride epitaxial structures.

Abstract: A semiconductor structure for forming FinFETs is described. The semiconductor structure includes a semiconductor substrate, a plurality of odd fins of the FinFETs on the substrate, and a plurality of even fins of the FinFETs on the substrate between the odd fins of the FinFETs. The odd fins of the FinFETs are defined from the substrate. The even fins of the FinFETs are different from the odd fins of the FinFETs in at least one of the width and the material, and may be further different from the odd fins of the FinFETs in the height.

Abstract: A method of forming a hybridized device comprising forming a first microelectronic component provided, on a surface, with metal balls, and a second microelectronic component provided, on a surface, with connection elements corresponding to said metal balls, and hybridizing the first and second components to attach the metal balls of the first component to the connection elements of the second component. The manufacturing of the second microelectronic component comprises forming a substrate provided with cavities at the locations provided for the connection elements, and forming resistive elements made of fusible metal respectively suspended above the cavities. The hybridizing of the first and second components comprises transferring the first component onto the second component to have the metal balls rest on the suspended resistive elements, and circulating an electric current through the resistive elements to melt said elements.

Abstract: Disclosed is a light-emitting device comprising: a semiconductor stack layer; a reflective layer on the semiconductor stack layer; a first buffer layer comprising a compound comprising a metallic element and a non-metallic element on the reflective layer; a first electrode; and an electrical insulating layer disposed between the first buffer layer and the first electrode.

Abstract: A double patterning method of forming a plurality of hole patterns having a small pitch using etch selectivities includes forming a patterning mask pattern defining a preliminary hole exposing an upper surface of a buffer mask layer, an inner spacer exposing the upper surface of the buffer mask layer on an inner wall of the preliminary hole, a buffer mask pattern having a first hole, and a core insulating pattern filling the preliminary hole and the first hole, an outer spacer to expose a first portion of the patterning mask pattern on the exposed portion of the outer side of the inner spacer, and an empty space exposing a first portion of the buffer mask pattern. A second portion of the patterning mask pattern and a second portion of the buffer mask pattern are exposed. A second hole is formed by removing the second portion of the buffer mask pattern.

Abstract: A method for etching features with different aspect ratios in an etch layer is provided. A plurality of cycles is provided wherein each cycle comprises a pre-etch transient conditioning of the etch layer, which provides a transient condition of the etch layer, wherein the transient condition has a duration and etching the etch layer for a duration, wherein the duration of the etching with respect to the duration of the transient condition is controlled to control etch aspect ratio dependence.

Abstract: Inverter logic devices include a gate oxide on a back substrate, a first graphene layer and a second graphene layer separated from each other on the gate oxide, a first electrode layer and a first semiconductor layer separated from each other on the first graphene layer, a second electrode layer and a second semiconductor layer separated from each other on the second graphene layer, and an output electrode on the first and second semiconductor layers and configured to output an output signal. The first semiconductor layer is doped with a different type of impurities selected from n-type impurities and p-type impurities than the second semiconductor layer.

Abstract: The disclosure relates to a semiconductor device. An exemplary structure for a contact structure for a semiconductor device comprises a substrate comprising a major surface and a cavity below the major surface; a strained material in the cavity, wherein a lattice constant of the strained material is different from a lattice constant of the substrate; a Ge-containing dielectric layer over the strained material; and a metal layer over the Ge-containing dielectric layer.

Abstract: Disclosed is a light-emitting diode, which has a red and infrared emitting wavelength, excellent monochromatism characteristics, and high output and high efficiency and excellent humidity resistance. The light-emitting diode is provided with: a light-emitting section, which includes an active layer having a quantum well structure and formed by laminating alternately a well layer which comprises a composition expressed by the composition formula of (AlX1Ga1-X1)As (0?X1?1) and a barrier layer which comprises a composition expressed by the composition formula of (AlX2Ga1-X2)As (0<X2?1), and a first clad layer and a second clad layer, between both of which the active layer is sandwiched, wherein the first clad layer and the second clad layer comprise a composition expressed by the composition formula of (AlX3Ga1-X3)Y1In1-Y1P (0?X3?1, 0<Y1?1); a current diffusion layer formed on the light-emitting section; and a functional substrate bonded to the current diffusion layer.

Abstract: Described is a lateral field emission device emitting electrons in parallel with respect to a substrate. Electron emission materials having a predetermined thickness are arranged in a direction with respect to the substrate on a supporting portion. An anode is disposed on a side portion of the substrate, the anode corresponding to the electron emission materials.

Abstract: Semiconductor devices are provided. The semiconductor devices may include an isolation pattern and first, second, and third active regions of a substrate. The first active region may be spaced apart from the second active region by a first width of the isolation pattern in a direction. A gate structure may be between the first and second active regions and may include a second width wider than the first width of the isolation pattern in the direction. Related methods of forming semiconductor devices are also provided.

Abstract: A nonvolatile memory device includes a floating gate formed over a substrate; a contact plug formed on a first side of the floating gate and disposed parallel to the floating gate with a gap defined therebetween; and a spacer formed on a sidewall of the floating gate and filling the gap, wherein the contact plug and the floating gate have a sufficiently large overlapping area to enable the contact plug to operate as a control gate for the floating gate.