Patents Examined by Natalia A Gondarenko
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Patent number: 11605725Abstract: An insulated gate bipolar transistor and a fabrication method therefor, wherein the fabrication method for the insulated gate bipolar transistor comprises the following steps: implanting hydrogen ions, arsenic ions, or nitrogen ions into a substrate from a back surface of the insulated gate bipolar transistor so as to form an n-type heavily doped layer (202) of a reverse conduction diode, the reverse conduction diode being a reverse conduction diode built into the insulated gate bipolar transistor. The described fabrication method and the obtained insulated gate bipolar transistor from a recombination center in an n+ junction of the reverse conduction diode, thereby accelerating the reverse recovery speed of the built-in reverse conduction diode, shortening the reverse recovery time thereof, and improving the performance of the insulated gate bipolar transistor.Type: GrantFiled: May 17, 2019Date of Patent: March 14, 2023Assignee: ADVANCED SEMICONDUCTOR MANUFACTURING CORPORATION., LTD.Inventors: Xueliang Wang, Jianhua Liu, Jinrong Lang, Yaneng Min
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Patent number: 11605735Abstract: Semiconductor structure and a method for fabricating the semiconductor structure are provided. The semiconductor structure includes a substrate, a doped source layer formed in the substrate; a channel pillar formed on the doped source layer; a gate structure formed on the sidewall surface of the channel pillar; a first contact layer, having a first thickness and formed at the surface of the doped source layer; and a second contact layer having a second thickness and formed on the top surface of the channel pillar. The first thickness is greater than the second thickness.Type: GrantFiled: August 14, 2020Date of Patent: March 14, 2023Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATIONInventor: Fei Zhou
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Patent number: 11600730Abstract: A transient voltage suppressor is disclosed that includes an electrode, a substrate disposed on the electrode, the substrate having a first doping, an epitaxial layer disposed on the substrate, the epitaxial layer having a second doping that is different from the first doping, a channel formed in the epitaxial layer having a width W, a length L and a plurality of curved regions, the channel forming a plurality of adjacent sections, the channel having a third doping that is different from the first doping and the second doping and a metal layer formed on top of the channel and contained within the width W of the channel.Type: GrantFiled: December 3, 2020Date of Patent: March 7, 2023Assignee: MICROSS CORPUS CHRISTI CORPORATIONInventor: David Francis Courtney
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Patent number: 11600615Abstract: A method of forming a semiconductor device includes forming a first vertical protection device comprising a thyristor in a substrate, forming a first lateral trigger element for triggering the first vertical protection device in the substrate, and forming an electrical path in the substrate to electrically couple the first lateral trigger element with the first vertical protection device.Type: GrantFiled: July 2, 2020Date of Patent: March 7, 2023Assignee: Infineon Technologies AGInventors: Vadim Valentinovic Vendt, Joost Adriaan Willemen, Andre Schmenn, Damian Sojka
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Patent number: 11594625Abstract: Described herein are III-N (e.g. GaN) devices having a stepped cap layer over the channel of the device, for which the III-N material is orientated in an N-polar orientation.Type: GrantFiled: February 26, 2020Date of Patent: February 28, 2023Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIAInventors: Matthew Guidry, Stacia Keller, Umesh K. Mishra, Brian Romanczyk, Xun Zheng
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Patent number: 11595036Abstract: Fin field-effect transistor (FinFET) thyristors for protecting high-speed communication interfaces are provided. In certain embodiments herein, high voltage tolerant FinFET thyristors are provided for handling high stress current and high RF power handling capability while providing low capacitance to allow wide bandwidth operation. Thus, the FinFET thyristors can be used to provide electrical overstress protection for ICs fabricated using FinFET technologies, while addressing tight radio frequency design window and robustness. In certain implementations, the FinFET thyristors include a first thyristor, a FinFET triggering circuitry and a second thyristor that serves to provide bidirectional blocking voltage and overstress protection. The FinFET triggering circuitry also enhances turn-on speed of the thyristor and/or reduces total on-state resistance.Type: GrantFiled: April 30, 2020Date of Patent: February 28, 2023Assignee: Analog Devices, Inc.Inventors: Javier A. Salcedo, Jonathan G. Pfeifer
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Patent number: 11574919Abstract: Embodiments of semiconductor devices and methods for forming the semiconductor devices are disclosed. In an example, a method for forming device openings includes forming a material layer over a first region and a second region of a substrate, the first region being adjacent to the second region, forming a mask layer over the material layer, the mask layer covering the first region and the second region, and forming a patterning layer over the mask layer. The patterning layer covers the first region and the second region and including openings corresponding to the first region. The plurality of openings includes a first opening adjacent to a boundary between the first region and the second region and a second opening further away from the boundary. Along a plane parallel to a top surface of the substrate, a size of the first opening is greater than a size of the second opening.Type: GrantFiled: September 10, 2020Date of Patent: February 7, 2023Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Jia He, Haihui Huang, Fandong Liu, Yaohua Yang, Peizhen Hong, Zhiliang Xia, Zongliang Huo, Yaobin Feng, Baoyou Chen, Qingchen Cao
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Patent number: 11575033Abstract: The present invention relates to a method for assembling molecules on the surface of a two-dimensional material formed on a substrate, the method comprises: forming a spacer layer comprising at least one of an electrically insulating compound or a semiconductor compound on the surface of the two-dimensional material, depositing molecules on the spacer layer, annealing the substrate with spacer layer and the molecules at an elevated temperature for an annealing time duration, wherein the temperature and annealing time are such that at least a portion of the molecules are allowed to diffuse through the spacer layer towards the surface of the two-dimensional material to assemble on the surface of the two-dimensional material. The invention also relates to an electronic device.Type: GrantFiled: December 6, 2018Date of Patent: February 7, 2023Assignee: GRAPHENSIC ABInventors: Samuel Lara-Avila, Hans He, Sergey Kubatkin
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Patent number: 11575029Abstract: Disclosed is a semiconductor structure including at least one bipolar junction transistor (BJT), which is uniquely configured so that fabrication of the BJT can be readily integrated with fabrication of complementary metal oxide semiconductor (CMOS) devices on an advanced silicon-on-insulator (SOI) wafer. The BJT has an emitter, a base, and a collector laid out horizontally across an insulator layer and physically separated. Extension regions extend laterally between the emitter and the base and between the base and the collector and are doped to provide junctions between the emitter and the base and between the base and the collector. Gate structures are on the extension regions. The emitter, base, and collector are contacted. Optionally, the gate structures and a substrate below the insulator layer are contacted and can be biased to optimize BJT performance. Optionally, the structure further includes one or more CMOS devices. Also disclosed is a method of forming the structure.Type: GrantFiled: May 19, 2021Date of Patent: February 7, 2023Assignee: GlobalFoundries U.S. Inc.Inventors: Alexander M. Derrickson, Richard F. Taylor, III, Mankyu Yang, Alexander L. Martin, Judson R. Holt, Jagar Singh
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Patent number: 11569371Abstract: We disclose herein a gate controlled bipolar semiconductor device comprising: a collector region of a first conductivity type; a drift region of a second conductivity type located over the collector region; a body region of a first conductivity type located over the drift region; a plurality of first contact regions of a second conductivity type located above the body region and having a higher doping concentration than the body region; a second contact region of a first conductivity type located laterally adjacent to the plurality of first contact regions, the second contact region having a higher doping concentration than the body region; at least two active trenches each extending from a surface into the drift region; an emitter trench extending from the surface into the drift region; wherein each first contact region adjoins an active trench so that, in use, a channel is formed along said each active trench and within the body region; wherein the second contact region adjoins the emitter trench; and whereType: GrantFiled: May 25, 2017Date of Patent: January 31, 2023Assignees: DYNEX SEMICONDUCTOR LIMITED, ZHUZHOU CRRC TIMES ELECTRIC CO. LTD.Inventors: Ian Deviny, Luther-King Ngwendson, John Hutchings
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Patent number: 11563115Abstract: According to the embodiment of the invention, the semiconductor device includes a semiconductor member, a first electrode, a second electrode, a third electrode, a first conductive member, and a first insulating member. The first semiconductor member includes a first semiconductor region, a second semiconductor region, and a third semiconductor region. The second semiconductor region includes one of a first material and a second material. The third semiconductor region is provided between at least a part of the first semiconductor region and the second semiconductor region. The first electrode is electrically connected with the first semiconductor region. The second electrode is electrically connected with the second semiconductor region. At least a part of the third semiconductor region is between an other portion of the third electrode and the first conductive member. At least a part of the first insulating member is between the third electrode and the semiconductor member.Type: GrantFiled: January 15, 2021Date of Patent: January 24, 2023Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Matthew David Smith, Akira Mukai, Masahiko Kuraguchi
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Patent number: 11552093Abstract: A 3D NAND flash memory device includes a substrate, a source line on the substrate, a stacked structure on the source line, a bit line on the stacked structure, and a columnar channel portion. The stacked structure includes a first select transistor, memory cells, and a second select transistor, wherein the first select transistor includes a first select gate, the memory cells include control gates, and the second select transistor includes a second select gate. The columnar channel portion is extended axially from the source line and penetrates the stacked structure to be coupled to the bit line. The first select transistor includes a modified Schottky barrier (MSB) transistor to generate direct tunneling of majority carriers to the columnar channel portion to perform a program operation or an erase operation.Type: GrantFiled: November 19, 2020Date of Patent: January 10, 2023Assignee: Powerchip Semiconductor Manufacturing CorporationInventor: Zih-Song Wang
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Patent number: 11552184Abstract: The disclosure provides a superjunction IGBT (insulated gate bipolar transistor) device, wherein a carrier storage layer of a first conductivity type is provided between a voltage sustaining layer and a base region, and a MISFET (metal-insulator-semiconductor field effect transistor) of a second conductivity type is also integrated in a cell, with at least one gate of the MISFET is connected to the emitter contact thereof. The MISFET is turned off at a low forward conduction voltage, helping to reduce the conduction voltage drop. The MISFET can provide a path for carriers of a second conductivity type and prevent the carrier storage layer from suffering a high electric field when the forward conduction voltage is slightly higher or it is at the forward blocking state, helping to improve the reliability.Type: GrantFiled: October 20, 2020Date of Patent: January 10, 2023Assignee: SICHUAN UNIVERSITYInventor: Mingmin Huang
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Patent number: 11552188Abstract: A semiconductor structure includes a substrate, a semiconductor epitaxial layer, a semiconductor barrier layer, a first semiconductor device, a doped isolation region, and at least one isolation pillar. The substrate includes a core layer and a composite material layer, the semiconductor epitaxial layer is disposed on the substrate, and the semiconductor barrier layer is disposed on the semiconductor epitaxial layer. The first semiconductor device is disposed on the substrate, where the first semiconductor device includes a first semiconductor cap layer disposed on the semiconductor barrier layer. The doped isolation region is disposed at one side of the first semiconductor device. At least a portion of the isolation pillar is disposed in the doped isolation region, and the isolation pillar surrounds at least a portion of the first semiconductor device and penetrates the composite material layer.Type: GrantFiled: November 24, 2020Date of Patent: January 10, 2023Assignee: Vanguard International Semiconductor CorporationInventors: Yu-Chieh Chou, Tsung-Hsiang Lin
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Patent number: 11537019Abstract: A novel composite oxide semiconductor which can be used in a transistor including an oxide semiconductor film is provided. In the composite oxide semiconductor, a first region and a second region are mixed. The first region includes a plurality of first clusters containing In and oxygen as main components. The second region includes a plurality of second clusters containing Zn and oxygen as main components. The plurality of first clusters have portions connected to each other. The plurality of second clusters have portions connected to each other.Type: GrantFiled: January 19, 2021Date of Patent: December 27, 2022Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Shunpei Yamazaki
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Patent number: 11532573Abstract: A semiconductor device is disclosed. The semiconductor device includes a first die on a first substrate, a second die on a second substrate separate from the first substrate, a transmission line in a redistribution layer on a wafer, and a magnetic structure surrounds the transmission line. The first transmission line electrically connects the first die and the second die. The magnetic structure is configured to increase the characteristic impedance of the transmission line, which can save the current and power consumption of a current mirror and amplifier in a 3D IC chip-on-wafer-on-substrate (CoWoS) semiconductor package.Type: GrantFiled: May 13, 2020Date of Patent: December 20, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Wen-Shiang Liao, Huan-Neng Chen
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Patent number: 11527627Abstract: A semiconductor Schottky rectifier built in an epitaxial semiconductor layer over a substrate has an anode structure and a cathode structure extending from the surface of the epitaxial layer. The cathode contact structure has a trench structure near the epi-layer and a vertical sidewall surface covered with a gate oxide layer. The cathode structure further comprises a polysilicon element adjacent to the gate oxide layer.Type: GrantFiled: July 7, 2020Date of Patent: December 13, 2022Assignee: Diodes IncorporatedInventors: Kolins Chao, John Huang
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Patent number: 11522076Abstract: A field effect transistor (FET), a method of fabricating a field effect transistor, and an electronic device, the field effect transistor comprises: a source and a drain, the source being made of a first graphene film; a channel disposed between the source and the drain, and comprising a laminate of a second graphene film and a material layer having semiconductor properties, the second graphene film being formed of bilayer graphene; and a gate disposed on the laminate and electrically insulated from the laminate.Type: GrantFiled: October 17, 2018Date of Patent: December 6, 2022Assignees: BEIJING HUA TAN YUAN XIN ELECTRONICS, BEIJING HUATAN TECHNOLOGY CO., LTD.Inventor: Shibo Liang
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Patent number: 11522077Abstract: Various embodiments of the present disclosure are directed towards an integrated chip a first undoped layer overlies a substrate. A first barrier layer overlies the first undoped layer and has a first thickness. A first doped layer overlies the first barrier layer and is disposed laterally within an n-channel device region of the substrate. A second barrier layer overlies the first barrier layer and is disposed within a p-channel device region that is laterally adjacent to the n-channel device region. The second barrier layer has a second thickness that is greater than the first thickness. A second undoped layer overlies the second barrier layer. A second doped layer overlies the second undoped layer. The second undoped layer and the second doped layer are disposed within the p-channel device region.Type: GrantFiled: May 27, 2020Date of Patent: December 6, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Man-Ho Kwan, Fu-Wei Yao, Chun Lin Tsai, Jiun-Lei Jerry Yu, Ting-Fu Chang
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Patent number: 11515409Abstract: The present invention relates to a semiconductor device with an asymmetric gate structure. The device comprises a substrate; a channel layer, positioned above the substrate; a barrier layer, positioned above the channel layer, the barrier layer and the channel layer being configured to form two-dimensional electron gas (2DEG), and the 2DEG being formed in the channel layer along an interface between the channel layer and the barrier layer; a source contact and a drain contact, positioned above the barrier layer; a doped group III-V layer, positioned above the barrier layer and between the drain contact and the source contact; and a gate electrode, positioned above the doped group III-V layer and configured to form a Schottky junction with the doped group III-V layer, wherein the doped group III-V layer and/or gate electrode has a non-central symmetrical geometry so as to achieve the effect of improving gate leakage current characteristics.Type: GrantFiled: October 7, 2020Date of Patent: November 29, 2022Assignee: INNOSCIENCE (ZHUHAI) TECHNOLOGY CO., LTD.Inventors: Hang Liao, Qiyue Zhao, Chang An Li, Chao Wang, Chunhua Zhou, King Yuen Wong