Abstract: A memory device includes a plurality of layers forming a stack. The plurality of layers include a spin polarization layer having a magnetic anisotropy approximately perpendicular to a plane of the spin polarization layer, an antiferromagnetic layer having an antiferromagnetic material, a ferromagnetic layer that is exchange coupled to the antiferromagnetic layer, where the antiferromagnetic layer is between the ferromagnetic layer and the spin polarization layer, and a storage layer having a magnetization direction that indicates a memory state of the storage layer. The memory state is switched by an amount of current through the stack. The spin polarization layer, the ferromagnetic layer, and the antiferromagnetic layer are configured to reduce the amount of current through the stack for switching the magnetization direction of the storage layer relative to an amount of current through a memory device without the spin polarization layer, the ferromagnetic layer, and the antiferromagnetic layer.

Abstract: A three-dimensional semiconductor device including a conductive layer disposed on a substrate and including a first conductivity-type impurity; an insulating base layer disposed on the conductive layer; a stack structure including a lower insulating film disposed on the insulating base layer, and a plurality of gate electrodes and a plurality of mold insulating layers alternately stacked on the lower insulating film, wherein the insulating base layer includes a high dielectric material; a vertical structure including a vertical channel layer penetrating through the stack structure and a vertical insulating layer disposed between the vertical channel layer and the plurality of gate electrodes, the vertical structure having an extended area extending in a width direction in the insulating base layer; and an isolation structure penetrating through the stack structure, the insulating base layer and the conductive layer, and extending in a direction parallel to an upper surface of the substrate, wherein the conduc

Abstract: A vertical power device is disclosed, the device having a top side and a bottom side, and the device comprising (i) a substrate; (ii) a layered group III-Nitride based device stack formed atop the substrate; (iii) a first vertical group III-Nitride based device and a second vertical group III-Nitride based device formed in the group III-Nitride based device stack, wherein the first vertical group III-Nitride based device and the second vertical group III-Nitride based device are electrically connected; and (iv) a first vertical device isolation structure that isolates the first vertical group III-Nitride based device from the second vertical group III-Nitride based device. Also disclosed are a vertical power system integrating vertical power devices and a process for fabricating a vertical power device.

Abstract: A stacked ESD structure comprises a heavily doped substrate; an epitaxial layer grown on the substrate; a trench formed in the epitaxial layer; an oxide layer formed on an inner sidewall of the trench; first and second poly layers formed in the trench; a plurality of P-type regions and N-type regions formed inside the first and second poly layers to make back to back diodes in the first and second poly layers respectively; a dielectric layer formed in the trench, between the first and second poly layers; an insulating layer formed on top of the second poly layer and the trench; a plurality of contact defined to connect the first poly layer, the poly resistor and the second poly layer, through the insulating layer; and a metal layer formed on top of the insulating layer.

Abstract: A semiconductor device that can detect temperature appropriately is provided. A semiconductor device provided with a semiconductor substrate in which one or more transistor portions and one or more diode portions are provided is provided, including: a temperature detecting portion provided above the top surface of the semiconductor substrate and having a longitudinal side in a predetermined longitudinal direction; a top surface electrode provided above the top surface of the semiconductor substrate; and one or more external lines that have a connecting part connected with the top surface electrode and electrically connect the top surface electrode to a circuit outside the semiconductor device. The temperature detecting portion extends across the one or more transistor portions and the one or more diode portions in the longitudinal direction, and the connecting part of at least one of the external lines is arranged around the temperature detecting portion when seen from above.

Abstract: A silicon-controlled-rectifier electrostatic protection structure and a fabrication method are provided. The structure includes: a substrate of P-type; a first N-type well, a second N-type well, and a third N-type well in the substrate; a first P-type doped region in the first N-type well; first N-type doped regions at sides of the first N-type well along a first direction; first gate structures on a portion of the first N-type doped regions and on a portion of the first P-type doped region; second gate structure groups at sides of the first N-type well along a second direction; second N-type doped regions in the substrate at sides of each second gate structure along the first direction; second P-type doped regions in the second N-type doped regions between adjacent second gate structure groups; and a third P-type doped region and a cathode N-type doped region in the substrate.

Abstract: A method of forming one or more contact regions in a high-voltage field effect transistor (HFET) includes providing a semiconductor material, including a first active layer and a second active layer, with a gate dielectric disposed on a surface of the semiconductor material. A first contact to the semiconductor material is formed that extends through the second active layer into the first active layer, and a passivation layer is deposited, where the gate dielectric is disposed between the passivation layer and the second active layer. An interconnect is formed extending through the first passivation layer and coupled to the first contact. An interlayer dielectric is deposited proximate to the interconnect, and a plug is formed extending into the interlayer dielectric and coupled to the first portion of the interconnect.

Abstract: A pixel array package structure includes: a substrate; a pixel array disposed on the substrate, in which the pixel array includes a plurality of light emitting diode chips, and the light emitting diode chips include at least one red diode chip, at least one green diode chip, at least one blue diode chip, and a combination thereof; a reflective layer disposed on the substrate and between any two adjacent of the light emitting diode chips; a light-absorbing layer disposed on the reflective layer and surrounding the pixel array; and a light-transmitting layer disposed on the pixel array, the reflective layer, and the light-absorbing layer, in which the light-transmitting layer has an upper surface and a lower surface opposite thereto, and the lower surface is in contact with the pixel array, and the upper surface has a roughness of 0.005 mm to 0.1 mm.

Abstract: A semiconductor device is disclosed. A semiconductor device according to an example of the present disclosure includes a gate electrode of a ring shape having an opening area on a substrate; a P-type deep well region formed in the opening area; a drain region formed on the P-type deep well region; an N-type well region overlapping with the gate electrode; a source region formed in the N-type well region; a bulk tab region formed by being isolated from the source region by a first isolation region; a P-type drift region formed in contact with the N-type well region; and a second isolation region formed near the bulk tab region.

Abstract: A semiconductor device structure and method of manufacturing a semiconductor device is provided. The method includes providing a first semiconductor substrate having a first major surface and an opposing second major surface, the first major surface having a first metal layer formed thereon; providing a second semiconductor substrate having a first major surface and an opposing second major surface, with the second semiconductor substrate including a plurality of active device regions formed therein and a second metal layer formed on the first major surface connecting each of the plurality of active device regions; bonding the first metal layer of the first semiconductor substrate to the second metal layer of the second semiconductor substrate; and forming device contacts on the second major surface of the second semiconductor substrate for electrical connection to each of the plurality of active device regions.

Abstract: An electronic device including a transistor structure, and a process of forming the electronic device can include providing a workpiece including a substrate, a first layer, and a channel layer including a compound semiconductor material; and implanting a species into the workpiece such that the projected range extends at least into the channel and first layers, and the implant is performed into an area corresponding to at least a source region of the transistor structure. In an embodiment, the area corresponds to substantially all area occupied by the transistor structure. In another embodiment, the implant can form crystal defects within layers between the substrate and source, gate, and drain electrodes. The crystal defects may allow resistive coupling between the substrate and the channel structure within the transistor structure. The resistive coupling allows for better dynamic on-state resistance and potentially other electrical properties.

Abstract: A transistor includes a substrate having a first surface and a second surface opposite the first surface, a drift region having a doped region on the first surface of the substrate and a graded doping region on the doped region, a semiconductor fin protruding from the graded doping region and comprising a metal compound layer at an upper portion of the semiconductor fin, a source metal contact on the metal compound layer, a gate layer having a bottom portion directly contacting the graded doping region; and a drain metal contact on the second surface of the substrate.

Abstract: A semiconductor device includes a semiconductor substrate, an upper diffusion region and a lower diffusion region. The semiconductor substrate has a main surface. The upper diffusion region of a first conductivity type is disposed close to the main surface of the semiconductor device. The lower diffusion region of a second conductivity type is disposed up to a position deeper than the upper diffusion region in a depth direction of the semiconductor substrate from the main surface as a reference, and has a higher impurity concentration than the semiconductor substrate. A diode device is provided by having a PN junction surface at an interface between the upper diffusion region and the lower diffusion region, and the PN junction surface has a curved surface disposed at a portion opposite to the main surface.

Abstract: A semiconductor device includes a ring-shaped gate electrode having an opening area disposed on a substrate, a source region and a bulk tap region disposed in the opening area, a well region disposed to overlap the ring-shaped gate electrode, a drift region disposed to be in contact with the well region, a first insulating isolation region disposed, on the drift region, to partially overlap the gate electrode, a second insulating isolation region enclosing the bulk tap region, a drain region disposed to be spaced apart from the ring-shaped gate electrode, and a deep trench isolation region disposed adjacent to the drain region.

Abstract: The present disclosure is related to a detection apparatus. The detection apparatus may include a gate insulating layer. The gate insulating layer may include at least a first layer and a second layer opposite the first layer. A plurality of protruding structures may be provided on a surface of the first layer facing the second layer and/or a surface of the second layer facing the first layer. The first layer and the second layer of the gate insulating layer may be connected through the protruding structures.

Abstract: A transistor manufacturing method includes forming a source electrode and a drain electrode on a substrate, forming a layer including an insulator layer to cover the source electrode and the drain electrode, and forming a gate electrode on the layer including the insulator layer, wherein the forming the gate electrode includes forming a plating base film, forming a protection layer of the plating base film, forming a photoresist layer on the protection layer to expose the photoresist layer with desired patterning light, causing the exposed photoresist layer to come into contact with a developer to remove the photoresist layer and the protection layer until the plating base film is uncovered corresponding to the patterning light, and after depositing a metal on the uncovered plating base film, causing an electroless plating solution to come into contact with the plating base film to perform electroless plating.

Abstract: This invention provides a nitride semiconductor light emitting device in which current concentration is suppressed without excessively increasing resistance at a low cost without increasing a manufacturing process. The planar shape of a mesa portion configuring a nitride semiconductor light emitting device is a shape containing a convex-shaped tip portion 352b formed by a curved line or a plurality of straight lines and abase portion 352a continuous to the convex-shaped tip portion 352b, in which an obtuse angle is formed by adjacent two straight lines in the convex-shaped tip portion formed by the plurality of straight lines. The first electrode layer 4 has visible outlines 411 and 412 along a visible outline 302 of the mesa portion through a gap 9 in planar view. The relationship between a gap W1 in the convex-shaped tip portion 352b and a gap W2 in the base portion 352a is W1>W2.

Abstract: A semiconductor memory device includes, a stack structure, and a channel structure passing through the stack structure, wherein the channel structure includes a channel layer passing through the stack structure and a memory layer surrounding the channel layer, the stack structure includes a gate contacting the channel layer, and the channel layer and the gate form a Schottky junction.

Abstract: Embodiments of a channel hole plug structure of 3D memory devices and fabricating methods thereof are disclosed. The memory device includes an alternating layer stack disposed on a substrate, an insulating layer disposed on the alternating dielectric stack, a channel hole extending vertically through the alternating dielectric stack and the insulating layer, a channel structure including a channel layer in the channel hole, and a channel hole plug in the insulating layer and above the channel structure. The channel hole plug is electrically connected with the channel layer. A projection of the channel hole plug in a lateral plane covers a projection of the channel hole in the lateral plane.

Abstract: The present application relates to a technical field of semiconductors, and discloses a device having a physically unclonable function, a method for manufacturing same, and a chip using same.