Abstract: According to an embodiment, a substrate with an electrode is a substrate with an electrode 32 for manufacturing an organic device 10 including a first electrode 14, an organic functional layer 16, and a second electrode 18. The substrate with an electrode includes a support substrate 34, a first electrode provided on an inner side of a device formation area DA on a surface 34a of the support substrate 34, and an antistatic conductive portion 36 provided on the surface described above and electrically connected to the first electrode.

Abstract: A semiconductor device includes a semiconductor substrate of a first conductivity type. The semiconductor substrate includes a first semiconductor region of a second conductivity type at a surface thereof, a second semiconductor region of the second conductivity type at the surface and surrounding the first semiconductor region, a third semiconductor region of the second conductivity type provided in the second semiconductor region at the surface and surrounding the first semiconductor region. The third semiconductor region has a concentration of a second conductivity type impurity higher than that of the second semiconductor region. A first insulating film is provided on a part of the first surface at which the second semiconductor region is provided. the first insulating film having an opening that exposes. A first electrode is provided on the first insulating film and electrically connected to the third semiconductor region via the opening.

Abstract: Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate, a memory stack, and a NAND memory string. The memory stack includes a plurality of interleaved gate conductive layers and gate-to-gate dielectric layers above the substrate. Each of the gate-to-gate dielectric layers includes a silicon oxynitride layer. The NAND memory string extends vertically through the interleaved gate conductive layers and gate-to-gate dielectric layers of the memory stack.

Abstract: A method of controlling an effective gate length in a vertical field effect transistor is provided. The method includes forming a vertical fin on a substrate, and forming a bottom spacer layer on the substrate adjacent to the vertical fin. The method further includes forming a dummy gate block adjacent to the vertical fin on the bottom spacer layer. The method further includes forming a top spacer adjacent to the vertical fin on the dummy gate block, and removing the dummy gate block to expose a portion of the vertical fin between the top spacer and bottom spacer layer. The method further includes forming an absorption layer on the exposed portion of the vertical fin. The method further includes heat treating the absorption layer and vertical fin to form a dopant modified absorption layer, and removing the dopant modified absorption layer.

Abstract: Disclosed are an array substrate and a manufacturing method therefor, a display panel and a display apparatus. The array substrate comprises several pixel units located on a base substrate and arranged in an array, with each of the pixel units comprising a thin-film transistor, and the thin-film transistor comprising a polycrystalline silicon active layer, wherein a length extension direction of a channel of the thin-film transistor is parallel to a pre-set direction; and the pre-set direction is a scanning direction of an excimer laser beam used when forming the polycrystalline silicon active layer.

Abstract: Integrated chips include vertically stacked channel layers, with a first stack in a first device region and a second stack in a second device region. A first dielectric layer is formed conformally on the vertically stacked channel layers in the first device region. A second dielectric layer is formed conformally on the vertically stacked channel layers in the second device region. Gate conductors are formed around the vertically stacked channel layers in both the first device region and the second device region, filling a space between surfaces of the respective first dielectric layer and second dielectric layer.

Abstract: An image capturing device is provided. The device comprises a photodiode including a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type, a third semiconductor region of the second conductivity type, an insulator arranged between the photodiode and the third semiconductor region and a channel stop region of the first conductivity type which covers a side and a bottom surface of the insulator. The channel stop region includes a fourth semiconductor region arranged between the insulator and the second semiconductor region and a fifth semiconductor region arranged between the insulator and the third semiconductor region. An impurity concentration in the fourth semiconductor region is higher than an impurity concentration in the fifth semiconductor region and the impurity concentration in the fifth semiconductor region is not less than an impurity concentration in the first semiconductor region.

Abstract: An organic light emitting diode comprises an anode; an organic layer disposed on the anode and including a plurality of phosphorescent light emitting layers; and a cathode disposed on the organic layer, wherein a phosphorescent light emitting layer having a highest degree of horizontal orientation of a dopant among the plurality of phosphorescent light emitting layers is disposed to be adjacent to the cathode, and wherein the anode includes a short reduction pattern which implements a narrow path.

Abstract: Provided is a semiconductor device with a diode and a silicon controlled rectifier (SCR) including a substrate having a first conductivity type, a well region having a second conductivity type, a first doped region having the first conductivity type, and a second doped region having the second conductivity type. The well region is disposed in the substrate. The first doped region is disposed in the substrate. The second doped region is disposed in the substrate. The well region and the first doped region form a first PN junction, the well region and the substrate form a second PN junction, and the substrate and the second doped region form a third junction. The first, second, and third PN junctions form the SCR, and the first doped region and the third PN junction form the diode.

Abstract: In a method of forming a gate-all-around field effect transistor (GAA FET), a fin structure is formed. The fin structure includes a plurality of stacked structures each comprising a dielectric layer, a CNT over the dielectric layer, a support layer over the CNT. A sacrificial gate structure is formed over the fin structure, an isolation insulating layer is formed, a source/drain opening is formed by patterning the isolation insulating layer, the support layer is removed from each of the plurality of stacked structures in the source/drain opening, and a source/drain contact layer is formed in the source/drain opening. The source/drain contact is formed such that the source/drain contact is in direct contact with only a part of the CNT and a part of the dielectric layer is disposed between the source/drain contact and the CNT.

Abstract: In an embodiment, a device includes: a conductive shield on a first dielectric layer; a second dielectric layer on the first dielectric layer and the conductive shield, the first and second dielectric layers surrounding the conductive shield, the second dielectric layer including: a first portion disposed along an outer periphery of the conductive shield; a second portion extending through a center region of the conductive shield; and a third portion extending through a channel region of the conductive shield, the third portion connecting the first portion to the second portion; a coil on the second dielectric layer, the coil disposed over the conductive shield; an integrated circuit die on the second dielectric layer, the integrated circuit die disposed outside of the coil; and an encapsulant surrounding the coil and the integrated circuit die, top surfaces of the encapsulant, the integrated circuit die, and the coil being level.

Abstract: A power device, comprising, a semiconductor substrate composition having a substrate layer of a first conductivity type, one or more lateral double diffused metal oxide semiconductor (LDMOS) devices formed in the substrate layer. LDMOS structures are integrated in to the isolation region of a high voltage well. Each LDMOS is isolated from a power device substrate area by an isolator structure formed from the substrate layer. Each LDMOS comprises a continuous field plate formed at least partially on the thick insulation layer over each of the one or more LDMOS devices and in conductive contact with the power device substrate area.

Abstract: Methods of forming semiconductor devices include patterning a stack of layers that includes channel layers, n-type doped first sacrificial layers between the channel layers, and carbon-doped second sacrificial layers between the channel layers and the first sacrificial layers, to form one or more device regions. The first sacrificial layers and the second sacrificial layers are recessed relative to the channel layers with distinct respective etches to produce a flat, continuous, and vertical surface from sidewalls of the first sacrificial layers and respective second sacrificial layers. Inner spacers are formed in recesses formed by the recessing of the first sacrificial layers and the second sacrificial layers. The first sacrificial layers and the second sacrificial layers are etched away to leave the channel layers suspended.

Abstract: Disclosed is a quantum-confined Stark effect (QCSE) modulator. In the modulator, a first doped semiconductor region has a first type conductivity, is at the bottom of a trench in a dielectric layer and is immediately adjacent to a semiconductor layer. An MQW region is in the trench on the first doped semiconductor region and at least upper segments of sidewalls of the MQW region are angled away from adjacent sidewalls of the trench such that there are spaces between the MQW region and the dielectric layer. Dielectric spacers fill the spaces. A second doped semiconductor region has a second type conductivity, is on top of the MQW region and optionally extends laterally onto the tops of the dielectric spacers. The spacers prevent shorting of the doped semiconductor regions. Also disclosed are embodiments of a photonics structure including the modulator and of methods for forming the modulator and the photonics structure.

Abstract: A delocalizer and a light emitting device using the same are provided. The light emitting device includes a substrate and a first electrode layer. The first electrode layer is disposed over the substrate, in which two sides of the first electrode layer have a first contact pad and a second contact pad, respectively. The delocalizer is disposed between the first contact pad and the second contact pad. The delocalizer may include a plurality of strip-shaped transparent conductive members adjacent to each other, and a plurality of transparent conductive blocks adjacent to each other may be disposed between adjacent two of the strip-shaped transparent conductive members.

Abstract: A high-electron mobility transistor includes a substrate; a buffer layer over the substrate; a GaN channel layer over the buffer layer; a AlGaN layer over the GaN channel layer; a gate recess in the AlGaN layer; a source region and a drain region on opposite sides of the gate recess; a GaN source layer and a GaN drain layer grown on the AlGaN layer within the source region and the drain region, respectively; and a p-GaN gate layer in and on the gate recess.

Abstract: A display device includes a display area, a peripheral area, a pad portion, a bending area, a first crack detection circuit, and a first crack detection line. The display area includes pixels and data lines. The peripheral area is disposed outside the display area. The pad portion is disposed in the peripheral area. The bending area is disposed in the peripheral area. The bending area is bendable or in a bent state. The first crack detection circuit is disposed between the display area and the pad portion. The first crack detection circuit includes switches. The first crack detection line includes a first curved portion disposed in the bending area. The first crack detection line is connected between the pad portion and the first crack detection circuit.

Abstract: An organic light emitting display apparatus can include a substrate including a display area and a bending area; a pixel array layer including a driving wiring in the display area, and a thin film transistor electrically connected to the driving wiring; a planarization layer covering the pixel array layer; a light emitting device layer disposed on the planarization layer, the light emitting device layer being electrically connected to the thin film transistor; a routing wiring disposed in the bending area, the routing wiring being electrically connected to the driving wiring; a wiring contact part including a contact hole for electrically connecting the driving wiring to the routing wiring; and an encapsulation layer covering the light emitting device layer and the wiring contact part.

Abstract: A light emitting element includes: a semiconductor structure including: a substrate, an n-side nitride semiconductor layer containing an n-type impurity and located on the substrate, and a p-side nitride semiconductor layer containing a p-type impurity and located on the n-side nitride semiconductor layer, wherein a resistance of a peripheral portion of the p-side nitride semiconductor layer is higher than a resistance of an area inside of the peripheral portion in a top view, wherein a p-side nitride semiconductor side of the semiconductor structure is a light extraction face side, and an n-side nitride semiconductor side of the semiconductor structure is a mounting face side; and first protective layer located on an upper face of the p-side nitride semiconductor layer in a region corresponding to the peripheral portion of the p-side nitride semiconductor layer.

Abstract: A long-wavelength light emitting device is disclosed. The long-wavelength light emitting device comprises: a first conductive semi-conductor layer; an active layer that is located on the first conductive semi-conductor layer and that has a quantum well structure; and a second conductive semi-conductor layer that is located on the active layer. The active layer comprises: one or more well layers including a nitride-based semi-conductor having 21% or more In; two barrier layers located in upper and lower parts of the well layers, and located between the well layers and the barrier layers, wherein the upper capping layers have a bigger band-gap energy relative to the barrier layers, and the upper capping layers and the well layers are in contact.