Abstract: A semiconductor device includes: a substrate; a circuit element disposed on a first surface side of the substrate; a first transmission line disposed on the first surface side; a first terminal disposed on the first surface side; a first dielectric disposed in a part of the first transmission line; a second terminal disposed on a side of the first dielectric opposite to the first transmission line; a second transmission line disposed on the first surface side and has one end coupled to the circuit element; a third terminal disposed on the first surface side and coupled to the other end of the second transmission line; a second dielectric disposed in a part of the second transmission line; a fourth terminal disposed on a side of the second dielectric opposite to the second transmission line; and a conductor disposed on a second surface side of the substrate.

Abstract: Transistors having reduced parasitics and enhanced performance. In some embodiments, a transistor can include a source and a drain each implemented as a first type active region, and a gate implemented relative to the source and the drain such that application of a voltage to the gate results in formation of a conductive channel between the source and the drain. The transistor can further include a body configured to provide the conductive channel upon the application of the voltage to the gate. The body can be implemented as a second type active region that butts with the first type active region on the source side at a respective area not covered by the gate, and does not butt with the first type active region on the drain side at a respective area not covered by the gate.

Abstract: Examples of the present technology include processing methods to incorporate stress in a channel region of a semiconductor transistor. The methods may include depositing a stressed material on an adjacent layer, where the adjacent layer is disposed between the stressed material and semiconductor material having an incorporated dopant. The adjacent layer may be characterized by an increased stress level after the deposition of the stressed material. The method may further include heating the stressed material and the adjacent layer, and removing the stressed material from the adjacent layer. The adjacent layer retains at least a portion of the increased stress after the removal of the stressed material. Examples of the present technology also include semiconductor structures having a conductive layer with first stress, and an intermediate layer with second stress in contact with the conductive layer. The second tensile stress may be at least ten times the first tensile stress.

Abstract: A high electron mobility transistor (HEMT) and method for forming the same are disclosed. The high electron mobility transistor includes a substrate, a mesa structure disposed on the substrate, a passivation layer disposed on the mesa structure, and at least a contact structure disposed in the passivation and the mesa structure. The mesa structure includes a channel layer and a barrier layer disposed on the channel layer. The contact structure includes a body portion and a plurality of protruding portions. The body portion is through the passivation layer. The protruding portions connect to a bottom surface of the body portion and through the barrier layer and a portion of the channel layer.

Abstract: A non-volatile memory cell is described. The non-volatile memory cell includes a substrate, insulators, a floating gate and a control gate. The substrate has a first fin and a second fin, wherein the second fin is located at a first side of the first fin and a conductive type of the second fin is different from that of the first fin. The insulators are located over the substrate, wherein the first fin and the second fin are respectively located between the insulators. The floating gate is located over the first fin, the insulators and the second fin. The control gate includes the second fin.

Abstract: A device emitting mid-infrared light that comprises a semiconductor substrate of GaSb or closely related material. The device can also comprise epitaxial heterostructures of InAs, GaAs, AlSb, and related alloys forming light emitting structures cascaded by tunnel junctions. Further, the device can comprise light emission from the front, epitaxial side of the substrate.

Abstract: A semiconductor device is disclosed. A semiconductor device according to an example of the present disclosure includes a gate electrode of a ring shape having an opening area on a substrate; a P-type deep well region formed in the opening area; a drain region formed on the P-type deep well region; an N-type well region overlapping with the gate electrode; a source region formed in the N-type well region; a bulk tab region formed by being isolated from the source region by a first isolation region; a P-type drift region formed in contact with the N-type well region; and a second isolation region formed near the bulk tab region.

Abstract: A variable resistance memory device and a method of manufacturing the same, the variable resistance memory device including a substrate including a first memory region and a second memory region; a plurality of first memory cells on the first memory region; and a plurality of second memory cells on the second memory region, wherein each of the first memory cells includes a first resistance element and a selection element, each of the second memory cells includes a second resistance element, and a maximum value of a variable resistance of the second resistance element is less than a maximum value of a variable resistance of the first resistance element.

Abstract: A display device according to an embodiment of the present invention includes a display panel having a through hole in a display area including a plurality of pixels. The display panel includes a substrate, and an organic light-emitting diode including a first electrode provided above the substrate for each of the pixels, a second electrode provided over the plurality of pixels, and an organic electroluminescence layer arranged between the first electrode and the second electrode. The through hole penetrates at least the second electrode, and the second electrode includes an oxidized part exposed at an inner surface of the through hole.

Abstract: A method includes forming a patterned etching mask, which includes a plurality of strips, and etching a semiconductor substrate underlying the patterned etching mask to form a first plurality of semiconductor fins and a second plurality of semiconductor fins. The patterned etching mask is used as an etching mask in the etching. The method further includes etching the second plurality of semiconductor fins without etching the first plurality of semiconductor fins. An isolation region is then formed, and the first plurality of semiconductor fins has top portions protruding higher than a top surface of the isolation region.

Abstract: A display device includes a display area, a peripheral area, a pad portion, a bending area, a first crack detection circuit, and a first crack detection line. The display area includes pixels and data lines. The peripheral area is disposed outside the display area. The pad portion is disposed in the peripheral area. The bending area is disposed in the peripheral area. The bending area is bendable or in a bent state. The first crack detection circuit is disposed between the display area and the pad portion. The first crack detection circuit includes switches. The first crack detection line includes a first curved portion disposed in the bending area. The first crack detection line is connected between the pad portion and the first crack detection circuit.

Abstract: An IGBT and a manufacturing method therefor, wherein a target region in the IGBT is doped with first ions; the target region comprises at least one of a P-type substrate (11), a P-type well region (13), and a P-type source region (14); and the diffusion coefficient of the first ions is greater than the diffusion coefficients of boron ions. A PN junction formed by means of the present invention is a gradual junction, thereby improving breakdown voltage, shortening turn-off time, and improving anti-latch capability.

Abstract: A disclosed semiconductor device includes an electron transit layer; an electron supply layer disposed above the electron transit layer; a source electrode, a drain electrode, and a gate electrode, the source electrode, the drain electrode, and the gate electrode being disposed on the electron supply layer; a first capping layer disposed on the electron supply layer between the gate electrode and the drain electrode; and a negative charge generation layer disposed on the first capping layer, the negative charge generation layer being configured to generate a negative charge.

Abstract: A semiconductor structure and a manufacturing method thereof is provided.

Abstract: A method includes bonding a first and a second package component on a top surface of a third package component, and dispensing a polymer. The polymer includes a first portion in a space between the first and the third package components, a second portion in a space between the second and the third package components, and a third portion in a gap between the first and the second package components. A curing step is then performed on the polymer. After the curing step, the third portion of the polymer is sawed to form a trench between the first and the second package components.

Abstract: A resistor-transistor-logic (RTL) circuit with GaN structure, including a GaN layer, a AlGaN barrier layer on the GaN layer, multiple p-type doped GaN capping layers on the AlGaN barrier layer, wherein parts of the p-type doped GaN capping layers in a high-voltage region and in a low-voltage region convert the underlying GaN layer into gate depletion areas, the GaN layer not covered by the p-type doped GaN capping layers in a resistor region becomes a 2DEG resistor.

Abstract: A method includes bonding a first and a second package component on a top surface of a third package component, and dispensing a polymer. The polymer includes a first portion in a space between the first and the third package components, a second portion in a space between the second and the third package components, and a third portion in a gap between the first and the second package components. A curing step is then performed on the polymer. After the curing step, the third portion of the polymer is sawed to form a trench between the first and the second package components.

Abstract: The present disclosure relates to a graphene spin transistor for all-electrical operation at room temperature and a logic gate using the graphene Rashba spin transistor. A graphene spin transistor of the present disclosure provides a graphene spin FET (Field Effect Transistor) for all-electrical operation at room temperature without a magnetic field or a ferromagnetic electrode by utilizing the Rashba-Edelstein effect in the graphene or the spin Hall effect of a TMDC (Transition Metal Dichalcogenide) material in order to replace CMOS transistors and extend Moore's Law, and further provides a logic gate using the graphene Rashba spin transistor.

Abstract: An ESD protection device may be provided, including: a substrate including a first conductivity region and a second conductivity region arranged therein. The first conductivity region may include a first terminal region and a second terminal region electrically coupled with each other. The second conductivity region may include a third terminal region and a fourth terminal region electrically coupled with each other. The second conductivity region may further include a fifth terminal region electrically coupled with the first and second terminal regions. The fifth terminal region may be arranged laterally between the third terminal region and the fourth terminal region. The first conductivity region, the first terminal region, the third terminal region, and the fifth terminal region may have a first conductivity type. The second conductivity region, the second terminal region, and the fourth terminal region may have a second conductivity type different from the first conductivity type.

Abstract: An ESD protection device may include a substrate having first and second substrate layers, and first and second bridged regions. Each substrate layer may include first and second border regions and a middle region laterally therebetween. Each bridged region may be arranged within the middle region and a respective border region of the second substrate layer. The middle region of the second substrate layer may be laterally narrower than the middle region of the first substrate layer. Each border region of the second substrate layer may be partially arranged over the middle region of the first substrate layer and partially arranged over a respective border region of the first substrate layer. The border regions of the substrate layers, and the bridged regions may have a first conductivity type, and the middle regions of the substrate layers may have a second conductivity type different from the first conductivity type.